xref: /linux/Documentation/devicetree/bindings/clock/fsl,sai-clock.yaml (revision 53597deca0e38c30e6cd4ba2114fa42d2bcd85bb) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/clock/fsl,sai-clock.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Freescale SAI bitclock-as-a-clock
8
9maintainers:
10  - Michael Walle <michael@walle.cc>
11
12description: |
13  It is possible to use the BCLK or MCLK pin of a SAI module as a generic
14  clock output. Some SoC are very constrained in their pin multiplexer
15  configuration. E.g. pins can only be changed in groups. For example, on
16  the LS1028A SoC you can only enable SAIs in pairs. If you use only one SAI,
17  the second pins are wasted. Using this binding it is possible to use the
18  clock of the second SAI as a MCLK clock for an audio codec, for example.
19
20  This is a composite of a gated clock and a divider clock.
21
22properties:
23  compatible:
24    oneOf:
25      - items:
26          - enum:
27              - fsl,imx8mm-sai-clock
28              - fsl,imx8mn-sai-clock
29              - fsl,imx8mp-sai-clock
30          - const: fsl,imx8mq-sai-clock
31      - items:
32          - enum:
33              - fsl,imx8mq-sai-clock
34              - fsl,vf610-sai-clock
35
36  reg:
37    maxItems: 1
38
39  clocks:
40    minItems: 1
41    maxItems: 2
42
43  clock-names:
44    minItems: 1
45    items:
46      - const: bus
47      - const: mclk1
48
49  '#clock-cells':
50    maximum: 1
51
52allOf:
53  - if:
54      properties:
55        compatible:
56          contains:
57            const: fsl,vf610-sai-clock
58    then:
59      properties:
60        clocks:
61          maxItems: 1
62        clock-names: false
63
64required:
65  - compatible
66  - reg
67  - clocks
68  - '#clock-cells'
69
70additionalProperties: false
71
72examples:
73  - |
74    soc {
75        #address-cells = <2>;
76        #size-cells = <2>;
77
78        mclk: clock-mclk@f130080 {
79            compatible = "fsl,vf610-sai-clock";
80            reg = <0x0 0xf130080 0x0 0x80>;
81            #clock-cells = <0>;
82            clocks = <&parentclk>;
83        };
84    };
85