1*e577af82SMichael Walle# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*e577af82SMichael Walle%YAML 1.2 3*e577af82SMichael Walle--- 4*e577af82SMichael Walle$id: http://devicetree.org/schemas/clock/fsl,flexspi-clock.yaml# 5*e577af82SMichael Walle$schema: http://devicetree.org/meta-schemas/core.yaml# 6*e577af82SMichael Walle 7*e577af82SMichael Walletitle: Freescale FlexSPI clock driver for Layerscape SoCs 8*e577af82SMichael Walle 9*e577af82SMichael Wallemaintainers: 10*e577af82SMichael Walle - Michael Walle <michael@walle.cc> 11*e577af82SMichael Walle 12*e577af82SMichael Walledescription: 13*e577af82SMichael Walle The Freescale Layerscape SoCs have a special FlexSPI clock which is 14*e577af82SMichael Walle derived from the platform PLL. 15*e577af82SMichael Walle 16*e577af82SMichael Walleproperties: 17*e577af82SMichael Walle compatible: 18*e577af82SMichael Walle enum: 19*e577af82SMichael Walle - fsl,ls1028a-flexspi-clk 20*e577af82SMichael Walle - fsl,lx2160a-flexspi-clk 21*e577af82SMichael Walle 22*e577af82SMichael Walle reg: 23*e577af82SMichael Walle maxItems: 1 24*e577af82SMichael Walle 25*e577af82SMichael Walle clocks: 26*e577af82SMichael Walle maxItems: 1 27*e577af82SMichael Walle 28*e577af82SMichael Walle '#clock-cells': 29*e577af82SMichael Walle const: 0 30*e577af82SMichael Walle 31*e577af82SMichael Walle clock-output-names: 32*e577af82SMichael Walle maxItems: 1 33*e577af82SMichael Walle 34*e577af82SMichael Wallerequired: 35*e577af82SMichael Walle - compatible 36*e577af82SMichael Walle - reg 37*e577af82SMichael Walle - clocks 38*e577af82SMichael Walle - '#clock-cells' 39*e577af82SMichael Walle 40*e577af82SMichael WalleadditionalProperties: false 41*e577af82SMichael Walle 42*e577af82SMichael Walleexamples: 43*e577af82SMichael Walle - | 44*e577af82SMichael Walle dcfg { 45*e577af82SMichael Walle #address-cells = <1>; 46*e577af82SMichael Walle #size-cells = <1>; 47*e577af82SMichael Walle 48*e577af82SMichael Walle fspi_clk: clock-controller@900 { 49*e577af82SMichael Walle compatible = "fsl,ls1028a-flexspi-clk"; 50*e577af82SMichael Walle reg = <0x900 0x4>; 51*e577af82SMichael Walle #clock-cells = <0>; 52*e577af82SMichael Walle clocks = <&parentclk>; 53*e577af82SMichael Walle clock-output-names = "fspi_clk"; 54*e577af82SMichael Walle }; 55*e577af82SMichael Walle }; 56