1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/clock/brcm,iproc-clocks.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Broadcom iProc Family Clocks 8 9maintainers: 10 - Ray Jui <rjui@broadcom.com> 11 - Scott Branden <sbranden@broadcom.com> 12 13description: | 14 The iProc clock controller manages clocks that are common to the iProc family. 15 An SoC from the iProc family may have several PLLs, e.g., ARMPLL, GENPLL, 16 LCPLL0, MIPIPLL, and etc., all derived from an onboard crystal. Each PLL 17 comprises of several leaf clocks 18 19 ASIU clocks are a special case. These clocks are derived directly from the 20 reference clock of the onboard crystal. 21 22properties: 23 compatible: 24 enum: 25 - brcm,bcm63138-armpll 26 - brcm,cygnus-armpll 27 - brcm,cygnus-genpll 28 - brcm,cygnus-lcpll0 29 - brcm,cygnus-mipipll 30 - brcm,cygnus-asiu-clk 31 - brcm,cygnus-audiopll 32 - brcm,hr2-armpll 33 - brcm,nsp-armpll 34 - brcm,nsp-genpll 35 - brcm,nsp-lcpll0 36 - brcm,ns2-genpll-scr 37 - brcm,ns2-genpll-sw 38 - brcm,ns2-lcpll-ddr 39 - brcm,ns2-lcpll-ports 40 - brcm,sr-genpll0 41 - brcm,sr-genpll1 42 - brcm,sr-genpll2 43 - brcm,sr-genpll3 44 - brcm,sr-genpll4 45 - brcm,sr-genpll5 46 - brcm,sr-genpll6 47 - brcm,sr-lcpll0 48 - brcm,sr-lcpll1 49 - brcm,sr-lcpll-pcie 50 51 reg: 52 minItems: 1 53 items: 54 - description: base register 55 - description: power register 56 - description: ASIU or split status register 57 58 clocks: 59 description: The input parent clock phandle for the PLL / ASIU clock. For 60 most iProc PLLs, this is an onboard crystal with a fixed rate. 61 maxItems: 1 62 63 '#clock-cells': 64 const: 1 65 66 clock-output-names: 67 minItems: 1 68 maxItems: 45 69 70allOf: 71 - if: 72 properties: 73 compatible: 74 contains: 75 enum: 76 - brcm,cygnus-armpll 77 - brcm,cygnus-genpll 78 - brcm,cygnus-lcpll0 79 - brcm,cygnus-mipipll 80 - brcm,cygnus-asiu-clk 81 - brcm,cygnus-audiopll 82 then: 83 properties: 84 clock-output-names: 85 description: | 86 The following table defines the set of PLL/clock index and ID for Cygnus. 87 These clock IDs are defined in: 88 "include/dt-bindings/clock/bcm-cygnus.h" 89 90 Clock Source (Parent) Index ID 91 ----- --------------- ----- -- 92 crystal N/A N/A N/A 93 94 armpll crystal N/A N/A 95 96 keypad crystal (ASIU) 0 BCM_CYGNUS_ASIU_KEYPAD_CLK 97 adc/tsc crystal (ASIU) 1 BCM_CYGNUS_ASIU_ADC_CLK 98 pwm crystal (ASIU) 2 BCM_CYGNUS_ASIU_PWM_CLK 99 100 genpll crystal 0 BCM_CYGNUS_GENPLL 101 axi21 genpll 1 BCM_CYGNUS_GENPLL_AXI21_CLK 102 250mhz genpll 2 BCM_CYGNUS_GENPLL_250MHZ_CLK 103 ihost_sys genpll 3 BCM_CYGNUS_GENPLL_IHOST_SYS_CLK 104 enet_sw genpll 4 BCM_CYGNUS_GENPLL_ENET_SW_CLK 105 audio_125 genpll 5 BCM_CYGNUS_GENPLL_AUDIO_125_CLK 106 can genpll 6 BCM_CYGNUS_GENPLL_CAN_CLK 107 108 lcpll0 crystal 0 BCM_CYGNUS_LCPLL0 109 pcie_phy lcpll0 1 BCM_CYGNUS_LCPLL0_PCIE_PHY_REF_CLK 110 ddr_phy lcpll0 2 BCM_CYGNUS_LCPLL0_DDR_PHY_CLK 111 sdio lcpll0 3 BCM_CYGNUS_LCPLL0_SDIO_CLK 112 usb_phy lcpll0 4 BCM_CYGNUS_LCPLL0_USB_PHY_REF_CLK 113 smart_card lcpll0 5 BCM_CYGNUS_LCPLL0_SMART_CARD_CLK 114 ch5_unused lcpll0 6 BCM_CYGNUS_LCPLL0_CH5_UNUSED 115 116 mipipll crystal 0 BCM_CYGNUS_MIPIPLL 117 ch0_unused mipipll 1 BCM_CYGNUS_MIPIPLL_CH0_UNUSED 118 ch1_lcd mipipll 2 BCM_CYGNUS_MIPIPLL_CH1_LCD 119 ch2_v3d mipipll 3 BCM_CYGNUS_MIPIPLL_CH2_V3D 120 ch3_unused mipipll 4 BCM_CYGNUS_MIPIPLL_CH3_UNUSED 121 ch4_unused mipipll 5 BCM_CYGNUS_MIPIPLL_CH4_UNUSED 122 ch5_unused mipipll 6 BCM_CYGNUS_MIPIPLL_CH5_UNUSED 123 124 audiopll crystal 0 BCM_CYGNUS_AUDIOPLL 125 ch0_audio audiopll 1 BCM_CYGNUS_AUDIOPLL_CH0 126 ch1_audio audiopll 2 BCM_CYGNUS_AUDIOPLL_CH1 127 ch2_audio audiopll 3 BCM_CYGNUS_AUDIOPLL_CH2 128 - if: 129 properties: 130 compatible: 131 contains: 132 enum: 133 - brcm,hr2-armpll 134 then: 135 properties: 136 clock-output-names: 137 description: | 138 The following table defines the set of PLL/clock for Hurricane 2: 139 140 Clock Source Index ID 141 ----- ------ ----- -- 142 crystal N/A N/A N/A 143 144 armpll crystal N/A N/A 145 - if: 146 properties: 147 compatible: 148 contains: 149 enum: 150 - brcm,nsp-armpll 151 - brcm,nsp-genpll 152 - brcm,nsp-lcpll0 153 then: 154 properties: 155 clock-output-names: 156 description: | 157 The following table defines the set of PLL/clock index and ID for Northstar and 158 Northstar Plus. These clock IDs are defined in: 159 "include/dt-bindings/clock/bcm-nsp.h" 160 161 Clock Source Index ID 162 ----- ------ ----- -- 163 crystal N/A N/A N/A 164 165 armpll crystal N/A N/A 166 167 genpll crystal 0 BCM_NSP_GENPLL 168 phy genpll 1 BCM_NSP_GENPLL_PHY_CLK 169 ethernetclk genpll 2 BCM_NSP_GENPLL_ENET_SW_CLK 170 usbclk genpll 3 BCM_NSP_GENPLL_USB_PHY_REF_CLK 171 iprocfast genpll 4 BCM_NSP_GENPLL_IPROCFAST_CLK 172 sata1 genpll 5 BCM_NSP_GENPLL_SATA1_CLK 173 sata2 genpll 6 BCM_NSP_GENPLL_SATA2_CLK 174 175 lcpll0 crystal 0 BCM_NSP_LCPLL0 176 pcie_phy lcpll0 1 BCM_NSP_LCPLL0_PCIE_PHY_REF_CLK 177 sdio lcpll0 2 BCM_NSP_LCPLL0_SDIO_CLK 178 ddr_phy lcpll0 3 BCM_NSP_LCPLL0_DDR_PHY_CLK 179 - if: 180 properties: 181 compatible: 182 contains: 183 enum: 184 - brcm,ns2-genpll-scr 185 - brcm,ns2-genpll-sw 186 - brcm,ns2-lcpll-ddr 187 - brcm,ns2-lcpll-ports 188 then: 189 properties: 190 clock-output-names: 191 description: | 192 The following table defines the set of PLL/clock index and ID for Northstar 2. 193 These clock IDs are defined in: 194 "include/dt-bindings/clock/bcm-ns2.h" 195 196 Clock Source Index ID 197 ----- ------ ----- -- 198 crystal N/A N/A N/A 199 200 genpll_scr crystal 0 BCM_NS2_GENPLL_SCR 201 scr genpll_scr 1 BCM_NS2_GENPLL_SCR_SCR_CLK 202 fs genpll_scr 2 BCM_NS2_GENPLL_SCR_FS_CLK 203 audio_ref genpll_scr 3 BCM_NS2_GENPLL_SCR_AUDIO_CLK 204 ch3_unused genpll_scr 4 BCM_NS2_GENPLL_SCR_CH3_UNUSED 205 ch4_unused genpll_scr 5 BCM_NS2_GENPLL_SCR_CH4_UNUSED 206 ch5_unused genpll_scr 6 BCM_NS2_GENPLL_SCR_CH5_UNUSED 207 208 genpll_sw crystal 0 BCM_NS2_GENPLL_SW 209 rpe genpll_sw 1 BCM_NS2_GENPLL_SW_RPE_CLK 210 250 genpll_sw 2 BCM_NS2_GENPLL_SW_250_CLK 211 nic genpll_sw 3 BCM_NS2_GENPLL_SW_NIC_CLK 212 chimp genpll_sw 4 BCM_NS2_GENPLL_SW_CHIMP_CLK 213 port genpll_sw 5 BCM_NS2_GENPLL_SW_PORT_CLK 214 sdio genpll_sw 6 BCM_NS2_GENPLL_SW_SDIO_CLK 215 216 lcpll_ddr crystal 0 BCM_NS2_LCPLL_DDR 217 pcie_sata_usb lcpll_ddr 1 BCM_NS2_LCPLL_DDR_PCIE_SATA_USB_CLK 218 ddr lcpll_ddr 2 BCM_NS2_LCPLL_DDR_DDR_CLK 219 ch2_unused lcpll_ddr 3 BCM_NS2_LCPLL_DDR_CH2_UNUSED 220 ch3_unused lcpll_ddr 4 BCM_NS2_LCPLL_DDR_CH3_UNUSED 221 ch4_unused lcpll_ddr 5 BCM_NS2_LCPLL_DDR_CH4_UNUSED 222 ch5_unused lcpll_ddr 6 BCM_NS2_LCPLL_DDR_CH5_UNUSED 223 224 lcpll_ports crystal 0 BCM_NS2_LCPLL_PORTS 225 wan lcpll_ports 1 BCM_NS2_LCPLL_PORTS_WAN_CLK 226 rgmii lcpll_ports 2 BCM_NS2_LCPLL_PORTS_RGMII_CLK 227 ch2_unused lcpll_ports 3 BCM_NS2_LCPLL_PORTS_CH2_UNUSED 228 ch3_unused lcpll_ports 4 BCM_NS2_LCPLL_PORTS_CH3_UNUSED 229 ch4_unused lcpll_ports 5 BCM_NS2_LCPLL_PORTS_CH4_UNUSED 230 ch5_unused lcpll_ports 6 BCM_NS2_LCPLL_PORTS_CH5_UNUSED 231 - if: 232 properties: 233 compatible: 234 contains: 235 enum: 236 - brcm,sr-genpll0 237 - brcm,sr-genpll1 238 - brcm,sr-genpll2 239 - brcm,sr-genpll3 240 - brcm,sr-genpll4 241 - brcm,sr-genpll5 242 - brcm,sr-genpll6 243 - brcm,sr-lcpll0 244 - brcm,sr-lcpll1 245 - brcm,sr-lcpll-pcie 246 then: 247 properties: 248 clock-output-names: 249 description: | 250 The following table defines the set of PLL/clock index and ID for Stingray. 251 These clock IDs are defined in: 252 "include/dt-bindings/clock/bcm-sr.h" 253 254 Clock Source Index ID 255 ----- ------ ----- -- 256 crystal N/A N/A N/A 257 crmu_ref25m crystal N/A N/A 258 259 genpll0 crystal 0 BCM_SR_GENPLL0 260 clk_125m genpll0 1 BCM_SR_GENPLL0_125M_CLK 261 clk_scr genpll0 2 BCM_SR_GENPLL0_SCR_CLK 262 clk_250 genpll0 3 BCM_SR_GENPLL0_250M_CLK 263 clk_pcie_axi genpll0 4 BCM_SR_GENPLL0_PCIE_AXI_CLK 264 clk_paxc_axi_x2 genpll0 5 BCM_SR_GENPLL0_PAXC_AXI_X2_CLK 265 clk_paxc_axi genpll0 6 BCM_SR_GENPLL0_PAXC_AXI_CLK 266 267 genpll1 crystal 0 BCM_SR_GENPLL1 268 clk_pcie_tl genpll1 1 BCM_SR_GENPLL1_PCIE_TL_CLK 269 clk_mhb_apb genpll1 2 BCM_SR_GENPLL1_MHB_APB_CLK 270 271 genpll2 crystal 0 BCM_SR_GENPLL2 272 clk_nic genpll2 1 BCM_SR_GENPLL2_NIC_CLK 273 clk_ts_500_ref genpll2 2 BCM_SR_GENPLL2_TS_500_REF_CLK 274 clk_125_nitro genpll2 3 BCM_SR_GENPLL2_125_NITRO_CLK 275 clk_chimp genpll2 4 BCM_SR_GENPLL2_CHIMP_CLK 276 clk_nic_flash genpll2 5 BCM_SR_GENPLL2_NIC_FLASH_CLK 277 clk_fs genpll2 6 BCM_SR_GENPLL2_FS_CLK 278 279 genpll3 crystal 0 BCM_SR_GENPLL3 280 clk_hsls genpll3 1 BCM_SR_GENPLL3_HSLS_CLK 281 clk_sdio genpll3 2 BCM_SR_GENPLL3_SDIO_CLK 282 283 genpll4 crystal 0 BCM_SR_GENPLL4 284 clk_ccn genpll4 1 BCM_SR_GENPLL4_CCN_CLK 285 clk_tpiu_pll genpll4 2 BCM_SR_GENPLL4_TPIU_PLL_CLK 286 clk_noc genpll4 3 BCM_SR_GENPLL4_NOC_CLK 287 clk_chclk_fs4 genpll4 4 BCM_SR_GENPLL4_CHCLK_FS4_CLK 288 clk_bridge_fscpu genpll4 5 BCM_SR_GENPLL4_BRIDGE_FSCPU_CLK 289 290 genpll5 crystal 0 BCM_SR_GENPLL5 291 clk_fs4_hf genpll5 1 BCM_SR_GENPLL5_FS4_HF_CLK 292 clk_crypto_ae genpll5 2 BCM_SR_GENPLL5_CRYPTO_AE_CLK 293 clk_raid_ae genpll5 3 BCM_SR_GENPLL5_RAID_AE_CLK 294 295 genpll6 crystal 0 BCM_SR_GENPLL6 296 clk_48_usb genpll6 1 BCM_SR_GENPLL6_48_USB_CLK 297 298 lcpll0 crystal 0 BCM_SR_LCPLL0 299 clk_sata_refp lcpll0 1 BCM_SR_LCPLL0_SATA_REFP_CLK 300 clk_sata_refn lcpll0 2 BCM_SR_LCPLL0_SATA_REFN_CLK 301 clk_sata_350 lcpll0 3 BCM_SR_LCPLL0_SATA_350_CLK 302 clk_sata_500 lcpll0 4 BCM_SR_LCPLL0_SATA_500_CLK 303 304 lcpll1 crystal 0 BCM_SR_LCPLL1 305 clk_wan lcpll1 1 BCM_SR_LCPLL1_WAN_CLK 306 clk_usb_ref lcpll1 2 BCM_SR_LCPLL1_USB_REF_CLK 307 clk_crmu_ts lcpll1 3 BCM_SR_LCPLL1_CRMU_TS_CLK 308 309 lcpll_pcie crystal 0 BCM_SR_LCPLL_PCIE 310 clk_pcie_phy_ref lcpll1 1 BCM_SR_LCPLL_PCIE_PHY_REF_CLK 311 - if: 312 properties: 313 compatible: 314 contains: 315 const: brcm,cygnus-genpll 316 then: 317 properties: 318 clock-output-names: 319 items: 320 - const: genpll 321 - const: axi21 322 - const: 250mhz 323 - const: ihost_sys 324 - const: enet_sw 325 - const: audio_125 326 - const: can 327 - if: 328 properties: 329 compatible: 330 contains: 331 const: brcm,nsp-lcpll0 332 then: 333 properties: 334 clock-output-names: 335 items: 336 - const: lcpll0 337 - const: pcie_phy 338 - const: sdio 339 - const: ddr_phy 340 - if: 341 properties: 342 compatible: 343 contains: 344 const: brcm,nsp-genpll 345 then: 346 properties: 347 clock-output-names: 348 items: 349 - const: genpll 350 - const: phy 351 - const: ethernetclk 352 - const: usbclk 353 - const: iprocfast 354 - const: sata1 355 - const: sata2 356 357required: 358 - reg 359 - clocks 360 - '#clock-cells' 361 - clock-output-names 362 363additionalProperties: false 364 365examples: 366 - | 367 osc1: oscillator { 368 #clock-cells = <0>; 369 compatible = "fixed-clock"; 370 clock-frequency = <25000000>; 371 }; 372 373 genpll@301d000 { 374 #clock-cells = <1>; 375 compatible = "brcm,cygnus-genpll"; 376 reg = <0x301d000 0x2c>, <0x301c020 0x4>; 377 clocks = <&os1c>; 378 clock-output-names = "genpll", "axi21", "250mhz", "ihost_sys", 379 "enet_sw", "audio_125", "can"; 380 }; 381 - | 382 osc2: oscillator { 383 #clock-cells = <0>; 384 compatible = "fixed-clock"; 385 clock-frequency = <25000000>; 386 }; 387 388 asiu_clks@301d048 { 389 #clock-cells = <1>; 390 compatible = "brcm,cygnus-asiu-clk"; 391 reg = <0x301d048 0xc>, <0x180aa024 0x4>; 392 clocks = <&osc2>; 393 clock-output-names = "keypad", "adc/touch", "pwm"; 394 }; 395