1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/clock/brcm,iproc-clocks.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Broadcom iProc Family Clocks 8 9maintainers: 10 - Ray Jui <rjui@broadcom.com> 11 - Scott Branden <sbranden@broadcom.com> 12 13description: | 14 The iProc clock controller manages clocks that are common to the iProc family. 15 An SoC from the iProc family may have several PLLs, e.g., ARMPLL, GENPLL, 16 LCPLL0, MIPIPLL, and etc., all derived from an onboard crystal. Each PLL 17 comprises of several leaf clocks 18 19 ASIU clocks are a special case. These clocks are derived directly from the 20 reference clock of the onboard crystal. 21 22properties: 23 compatible: 24 enum: 25 - brcm,bcm63138-armpll 26 - brcm,cygnus-armpll 27 - brcm,cygnus-genpll 28 - brcm,cygnus-lcpll0 29 - brcm,cygnus-mipipll 30 - brcm,cygnus-asiu-clk 31 - brcm,cygnus-audiopll 32 - brcm,hr2-armpll 33 - brcm,nsp-armpll 34 - brcm,nsp-genpll 35 - brcm,nsp-lcpll0 36 - brcm,ns2-genpll-scr 37 - brcm,ns2-genpll-sw 38 - brcm,ns2-lcpll-ddr 39 - brcm,ns2-lcpll-ports 40 - brcm,sr-genpll0 41 - brcm,sr-genpll1 42 - brcm,sr-genpll2 43 - brcm,sr-genpll3 44 - brcm,sr-genpll4 45 - brcm,sr-genpll5 46 - brcm,sr-genpll6 47 - brcm,sr-lcpll0 48 - brcm,sr-lcpll1 49 - brcm,sr-lcpll-pcie 50 51 reg: 52 minItems: 1 53 maxItems: 3 54 items: 55 - description: base register 56 - description: power register 57 - description: ASIU or split status register 58 59 clocks: 60 description: The input parent clock phandle for the PLL / ASIU clock. For 61 most iProc PLLs, this is an onboard crystal with a fixed rate. 62 maxItems: 1 63 64 '#clock-cells': 65 true 66 67 clock-output-names: 68 minItems: 1 69 maxItems: 45 70 71allOf: 72 - if: 73 properties: 74 compatible: 75 contains: 76 enum: 77 - brcm,cygnus-armpll 78 - brcm,nsp-armpll 79 then: 80 properties: 81 '#clock-cells': 82 const: 0 83 else: 84 properties: 85 '#clock-cells': 86 const: 1 87 required: 88 - clock-output-names 89 - if: 90 properties: 91 compatible: 92 contains: 93 enum: 94 - brcm,cygnus-armpll 95 - brcm,cygnus-genpll 96 - brcm,cygnus-lcpll0 97 - brcm,cygnus-mipipll 98 - brcm,cygnus-asiu-clk 99 - brcm,cygnus-audiopll 100 then: 101 properties: 102 clock-output-names: 103 description: | 104 The following table defines the set of PLL/clock index and ID for Cygnus. 105 These clock IDs are defined in: 106 "include/dt-bindings/clock/bcm-cygnus.h" 107 108 Clock Source (Parent) Index ID 109 ----- --------------- ----- -- 110 crystal N/A N/A N/A 111 112 armpll crystal N/A N/A 113 114 keypad crystal (ASIU) 0 BCM_CYGNUS_ASIU_KEYPAD_CLK 115 adc/tsc crystal (ASIU) 1 BCM_CYGNUS_ASIU_ADC_CLK 116 pwm crystal (ASIU) 2 BCM_CYGNUS_ASIU_PWM_CLK 117 118 genpll crystal 0 BCM_CYGNUS_GENPLL 119 axi21 genpll 1 BCM_CYGNUS_GENPLL_AXI21_CLK 120 250mhz genpll 2 BCM_CYGNUS_GENPLL_250MHZ_CLK 121 ihost_sys genpll 3 BCM_CYGNUS_GENPLL_IHOST_SYS_CLK 122 enet_sw genpll 4 BCM_CYGNUS_GENPLL_ENET_SW_CLK 123 audio_125 genpll 5 BCM_CYGNUS_GENPLL_AUDIO_125_CLK 124 can genpll 6 BCM_CYGNUS_GENPLL_CAN_CLK 125 126 lcpll0 crystal 0 BCM_CYGNUS_LCPLL0 127 pcie_phy lcpll0 1 BCM_CYGNUS_LCPLL0_PCIE_PHY_REF_CLK 128 ddr_phy lcpll0 2 BCM_CYGNUS_LCPLL0_DDR_PHY_CLK 129 sdio lcpll0 3 BCM_CYGNUS_LCPLL0_SDIO_CLK 130 usb_phy lcpll0 4 BCM_CYGNUS_LCPLL0_USB_PHY_REF_CLK 131 smart_card lcpll0 5 BCM_CYGNUS_LCPLL0_SMART_CARD_CLK 132 ch5_unused lcpll0 6 BCM_CYGNUS_LCPLL0_CH5_UNUSED 133 134 mipipll crystal 0 BCM_CYGNUS_MIPIPLL 135 ch0_unused mipipll 1 BCM_CYGNUS_MIPIPLL_CH0_UNUSED 136 ch1_lcd mipipll 2 BCM_CYGNUS_MIPIPLL_CH1_LCD 137 ch2_v3d mipipll 3 BCM_CYGNUS_MIPIPLL_CH2_V3D 138 ch3_unused mipipll 4 BCM_CYGNUS_MIPIPLL_CH3_UNUSED 139 ch4_unused mipipll 5 BCM_CYGNUS_MIPIPLL_CH4_UNUSED 140 ch5_unused mipipll 6 BCM_CYGNUS_MIPIPLL_CH5_UNUSED 141 142 audiopll crystal 0 BCM_CYGNUS_AUDIOPLL 143 ch0_audio audiopll 1 BCM_CYGNUS_AUDIOPLL_CH0 144 ch1_audio audiopll 2 BCM_CYGNUS_AUDIOPLL_CH1 145 ch2_audio audiopll 3 BCM_CYGNUS_AUDIOPLL_CH2 146 - if: 147 properties: 148 compatible: 149 contains: 150 enum: 151 - brcm,hr2-armpll 152 then: 153 properties: 154 clock-output-names: 155 description: | 156 The following table defines the set of PLL/clock for Hurricane 2: 157 158 Clock Source Index ID 159 ----- ------ ----- -- 160 crystal N/A N/A N/A 161 162 armpll crystal N/A N/A 163 - if: 164 properties: 165 compatible: 166 contains: 167 enum: 168 - brcm,nsp-armpll 169 - brcm,nsp-genpll 170 - brcm,nsp-lcpll0 171 then: 172 properties: 173 clock-output-names: 174 description: | 175 The following table defines the set of PLL/clock index and ID for Northstar and 176 Northstar Plus. These clock IDs are defined in: 177 "include/dt-bindings/clock/bcm-nsp.h" 178 179 Clock Source Index ID 180 ----- ------ ----- -- 181 crystal N/A N/A N/A 182 183 armpll crystal N/A N/A 184 185 genpll crystal 0 BCM_NSP_GENPLL 186 phy genpll 1 BCM_NSP_GENPLL_PHY_CLK 187 ethernetclk genpll 2 BCM_NSP_GENPLL_ENET_SW_CLK 188 usbclk genpll 3 BCM_NSP_GENPLL_USB_PHY_REF_CLK 189 iprocfast genpll 4 BCM_NSP_GENPLL_IPROCFAST_CLK 190 sata1 genpll 5 BCM_NSP_GENPLL_SATA1_CLK 191 sata2 genpll 6 BCM_NSP_GENPLL_SATA2_CLK 192 193 lcpll0 crystal 0 BCM_NSP_LCPLL0 194 pcie_phy lcpll0 1 BCM_NSP_LCPLL0_PCIE_PHY_REF_CLK 195 sdio lcpll0 2 BCM_NSP_LCPLL0_SDIO_CLK 196 ddr_phy lcpll0 3 BCM_NSP_LCPLL0_DDR_PHY_CLK 197 - if: 198 properties: 199 compatible: 200 contains: 201 enum: 202 - brcm,ns2-genpll-scr 203 - brcm,ns2-genpll-sw 204 - brcm,ns2-lcpll-ddr 205 - brcm,ns2-lcpll-ports 206 then: 207 properties: 208 clock-output-names: 209 description: | 210 The following table defines the set of PLL/clock index and ID for Northstar 2. 211 These clock IDs are defined in: 212 "include/dt-bindings/clock/bcm-ns2.h" 213 214 Clock Source Index ID 215 ----- ------ ----- -- 216 crystal N/A N/A N/A 217 218 genpll_scr crystal 0 BCM_NS2_GENPLL_SCR 219 scr genpll_scr 1 BCM_NS2_GENPLL_SCR_SCR_CLK 220 fs genpll_scr 2 BCM_NS2_GENPLL_SCR_FS_CLK 221 audio_ref genpll_scr 3 BCM_NS2_GENPLL_SCR_AUDIO_CLK 222 ch3_unused genpll_scr 4 BCM_NS2_GENPLL_SCR_CH3_UNUSED 223 ch4_unused genpll_scr 5 BCM_NS2_GENPLL_SCR_CH4_UNUSED 224 ch5_unused genpll_scr 6 BCM_NS2_GENPLL_SCR_CH5_UNUSED 225 226 genpll_sw crystal 0 BCM_NS2_GENPLL_SW 227 rpe genpll_sw 1 BCM_NS2_GENPLL_SW_RPE_CLK 228 250 genpll_sw 2 BCM_NS2_GENPLL_SW_250_CLK 229 nic genpll_sw 3 BCM_NS2_GENPLL_SW_NIC_CLK 230 chimp genpll_sw 4 BCM_NS2_GENPLL_SW_CHIMP_CLK 231 port genpll_sw 5 BCM_NS2_GENPLL_SW_PORT_CLK 232 sdio genpll_sw 6 BCM_NS2_GENPLL_SW_SDIO_CLK 233 234 lcpll_ddr crystal 0 BCM_NS2_LCPLL_DDR 235 pcie_sata_usb lcpll_ddr 1 BCM_NS2_LCPLL_DDR_PCIE_SATA_USB_CLK 236 ddr lcpll_ddr 2 BCM_NS2_LCPLL_DDR_DDR_CLK 237 ch2_unused lcpll_ddr 3 BCM_NS2_LCPLL_DDR_CH2_UNUSED 238 ch3_unused lcpll_ddr 4 BCM_NS2_LCPLL_DDR_CH3_UNUSED 239 ch4_unused lcpll_ddr 5 BCM_NS2_LCPLL_DDR_CH4_UNUSED 240 ch5_unused lcpll_ddr 6 BCM_NS2_LCPLL_DDR_CH5_UNUSED 241 242 lcpll_ports crystal 0 BCM_NS2_LCPLL_PORTS 243 wan lcpll_ports 1 BCM_NS2_LCPLL_PORTS_WAN_CLK 244 rgmii lcpll_ports 2 BCM_NS2_LCPLL_PORTS_RGMII_CLK 245 ch2_unused lcpll_ports 3 BCM_NS2_LCPLL_PORTS_CH2_UNUSED 246 ch3_unused lcpll_ports 4 BCM_NS2_LCPLL_PORTS_CH3_UNUSED 247 ch4_unused lcpll_ports 5 BCM_NS2_LCPLL_PORTS_CH4_UNUSED 248 ch5_unused lcpll_ports 6 BCM_NS2_LCPLL_PORTS_CH5_UNUSED 249 - if: 250 properties: 251 compatible: 252 contains: 253 enum: 254 - brcm,sr-genpll0 255 - brcm,sr-genpll1 256 - brcm,sr-genpll2 257 - brcm,sr-genpll3 258 - brcm,sr-genpll4 259 - brcm,sr-genpll5 260 - brcm,sr-genpll6 261 - brcm,sr-lcpll0 262 - brcm,sr-lcpll1 263 - brcm,sr-lcpll-pcie 264 then: 265 properties: 266 clock-output-names: 267 description: | 268 The following table defines the set of PLL/clock index and ID for Stingray. 269 These clock IDs are defined in: 270 "include/dt-bindings/clock/bcm-sr.h" 271 272 Clock Source Index ID 273 ----- ------ ----- -- 274 crystal N/A N/A N/A 275 crmu_ref25m crystal N/A N/A 276 277 genpll0 crystal 0 BCM_SR_GENPLL0 278 clk_125m genpll0 1 BCM_SR_GENPLL0_125M_CLK 279 clk_scr genpll0 2 BCM_SR_GENPLL0_SCR_CLK 280 clk_250 genpll0 3 BCM_SR_GENPLL0_250M_CLK 281 clk_pcie_axi genpll0 4 BCM_SR_GENPLL0_PCIE_AXI_CLK 282 clk_paxc_axi_x2 genpll0 5 BCM_SR_GENPLL0_PAXC_AXI_X2_CLK 283 clk_paxc_axi genpll0 6 BCM_SR_GENPLL0_PAXC_AXI_CLK 284 285 genpll1 crystal 0 BCM_SR_GENPLL1 286 clk_pcie_tl genpll1 1 BCM_SR_GENPLL1_PCIE_TL_CLK 287 clk_mhb_apb genpll1 2 BCM_SR_GENPLL1_MHB_APB_CLK 288 289 genpll2 crystal 0 BCM_SR_GENPLL2 290 clk_nic genpll2 1 BCM_SR_GENPLL2_NIC_CLK 291 clk_ts_500_ref genpll2 2 BCM_SR_GENPLL2_TS_500_REF_CLK 292 clk_125_nitro genpll2 3 BCM_SR_GENPLL2_125_NITRO_CLK 293 clk_chimp genpll2 4 BCM_SR_GENPLL2_CHIMP_CLK 294 clk_nic_flash genpll2 5 BCM_SR_GENPLL2_NIC_FLASH_CLK 295 clk_fs genpll2 6 BCM_SR_GENPLL2_FS_CLK 296 297 genpll3 crystal 0 BCM_SR_GENPLL3 298 clk_hsls genpll3 1 BCM_SR_GENPLL3_HSLS_CLK 299 clk_sdio genpll3 2 BCM_SR_GENPLL3_SDIO_CLK 300 301 genpll4 crystal 0 BCM_SR_GENPLL4 302 clk_ccn genpll4 1 BCM_SR_GENPLL4_CCN_CLK 303 clk_tpiu_pll genpll4 2 BCM_SR_GENPLL4_TPIU_PLL_CLK 304 clk_noc genpll4 3 BCM_SR_GENPLL4_NOC_CLK 305 clk_chclk_fs4 genpll4 4 BCM_SR_GENPLL4_CHCLK_FS4_CLK 306 clk_bridge_fscpu genpll4 5 BCM_SR_GENPLL4_BRIDGE_FSCPU_CLK 307 308 genpll5 crystal 0 BCM_SR_GENPLL5 309 clk_fs4_hf genpll5 1 BCM_SR_GENPLL5_FS4_HF_CLK 310 clk_crypto_ae genpll5 2 BCM_SR_GENPLL5_CRYPTO_AE_CLK 311 clk_raid_ae genpll5 3 BCM_SR_GENPLL5_RAID_AE_CLK 312 313 genpll6 crystal 0 BCM_SR_GENPLL6 314 clk_48_usb genpll6 1 BCM_SR_GENPLL6_48_USB_CLK 315 316 lcpll0 crystal 0 BCM_SR_LCPLL0 317 clk_sata_refp lcpll0 1 BCM_SR_LCPLL0_SATA_REFP_CLK 318 clk_sata_refn lcpll0 2 BCM_SR_LCPLL0_SATA_REFN_CLK 319 clk_sata_350 lcpll0 3 BCM_SR_LCPLL0_SATA_350_CLK 320 clk_sata_500 lcpll0 4 BCM_SR_LCPLL0_SATA_500_CLK 321 322 lcpll1 crystal 0 BCM_SR_LCPLL1 323 clk_wan lcpll1 1 BCM_SR_LCPLL1_WAN_CLK 324 clk_usb_ref lcpll1 2 BCM_SR_LCPLL1_USB_REF_CLK 325 clk_crmu_ts lcpll1 3 BCM_SR_LCPLL1_CRMU_TS_CLK 326 327 lcpll_pcie crystal 0 BCM_SR_LCPLL_PCIE 328 clk_pcie_phy_ref lcpll1 1 BCM_SR_LCPLL_PCIE_PHY_REF_CLK 329 - if: 330 properties: 331 compatible: 332 contains: 333 const: brcm,cygnus-genpll 334 then: 335 properties: 336 clock-output-names: 337 items: 338 - const: genpll 339 - const: axi21 340 - const: 250mhz 341 - const: ihost_sys 342 - const: enet_sw 343 - const: audio_125 344 - const: can 345 - if: 346 properties: 347 compatible: 348 contains: 349 const: brcm,nsp-lcpll0 350 then: 351 properties: 352 clock-output-names: 353 items: 354 - const: lcpll0 355 - const: pcie_phy 356 - const: sdio 357 - const: ddr_phy 358 - if: 359 properties: 360 compatible: 361 contains: 362 const: brcm,nsp-genpll 363 then: 364 properties: 365 clock-output-names: 366 items: 367 - const: genpll 368 - const: phy 369 - const: ethernetclk 370 - const: usbclk 371 - const: iprocfast 372 - const: sata1 373 - const: sata2 374 375required: 376 - reg 377 - clocks 378 - '#clock-cells' 379 380additionalProperties: false 381 382examples: 383 - | 384 osc1: oscillator { 385 #clock-cells = <0>; 386 compatible = "fixed-clock"; 387 clock-frequency = <25000000>; 388 }; 389 390 genpll@301d000 { 391 #clock-cells = <1>; 392 compatible = "brcm,cygnus-genpll"; 393 reg = <0x301d000 0x2c>, <0x301c020 0x4>; 394 clocks = <&os1c>; 395 clock-output-names = "genpll", "axi21", "250mhz", "ihost_sys", 396 "enet_sw", "audio_125", "can"; 397 }; 398 - | 399 osc2: oscillator { 400 #clock-cells = <0>; 401 compatible = "fixed-clock"; 402 clock-frequency = <25000000>; 403 }; 404 405 asiu_clks@301d048 { 406 #clock-cells = <1>; 407 compatible = "brcm,cygnus-asiu-clk"; 408 reg = <0x301d048 0xc>, <0x180aa024 0x4>; 409 clocks = <&osc2>; 410 clock-output-names = "keypad", "adc/touch", "pwm"; 411 }; 412 - | 413 arm_clk@0 { 414 #clock-cells = <0>; 415 compatible = "brcm,nsp-armpll"; 416 clocks = <&osc>; 417 reg = <0x0 0x1000>; 418 }; 419