xref: /linux/Documentation/devicetree/bindings/clock/bitmain,bm1880-clk.yaml (revision 95298d63c67673c654c08952672d016212b26054) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/clock/bitmain,bm1880-clk.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Bitmain BM1880 Clock Controller
8
9maintainers:
10  - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
11
12description: |
13  The Bitmain BM1880 clock controller generates and supplies clock to
14  various peripherals within the SoC.
15
16  This binding uses common clock bindings
17  [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
18
19properties:
20  compatible:
21    const: bitmain,bm1880-clk
22
23  reg:
24    items:
25      - description: pll registers
26      - description: system registers
27
28  reg-names:
29    items:
30      - const: pll
31      - const: sys
32
33  clocks:
34    maxItems: 1
35
36  clock-names:
37    const: osc
38
39  '#clock-cells':
40    const: 1
41
42required:
43  - compatible
44  - reg
45  - reg-names
46  - clocks
47  - clock-names
48  - '#clock-cells'
49
50additionalProperties: false
51
52examples:
53  # Clock controller node:
54  - |
55    clk: clock-controller@e8 {
56        compatible = "bitmain,bm1880-clk";
57        reg = <0xe8 0x0c>, <0x800 0xb0>;
58        reg-names = "pll", "sys";
59        clocks = <&osc>;
60        clock-names = "osc";
61        #clock-cells = <1>;
62    };
63
64  # Example UART controller node that consumes clock generated by the clock controller:
65  - |
66    uart0: serial@58018000 {
67         compatible = "snps,dw-apb-uart";
68         reg = <0x58018000 0x2000>;
69         clocks = <&clk 45>, <&clk 46>;
70         clock-names = "baudclk", "apb_pclk";
71         interrupts = <0 9 4>;
72         reg-shift = <2>;
73         reg-io-width = <4>;
74    };
75
76...
77