xref: /linux/Documentation/devicetree/bindings/clock/bitmain,bm1880-clk.yaml (revision 4f2c0a4acffbec01079c28f839422e64ddeff004)
17046c6b0SManivannan Sadhasivam# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
27046c6b0SManivannan Sadhasivam%YAML 1.2
37046c6b0SManivannan Sadhasivam---
4*04dbd865SRob Herring$id: http://devicetree.org/schemas/clock/bitmain,bm1880-clk.yaml#
57046c6b0SManivannan Sadhasivam$schema: http://devicetree.org/meta-schemas/core.yaml#
67046c6b0SManivannan Sadhasivam
77046c6b0SManivannan Sadhasivamtitle: Bitmain BM1880 Clock Controller
87046c6b0SManivannan Sadhasivam
97046c6b0SManivannan Sadhasivammaintainers:
107046c6b0SManivannan Sadhasivam  - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
117046c6b0SManivannan Sadhasivam
127046c6b0SManivannan Sadhasivamdescription: |
137046c6b0SManivannan Sadhasivam  The Bitmain BM1880 clock controller generates and supplies clock to
147046c6b0SManivannan Sadhasivam  various peripherals within the SoC.
157046c6b0SManivannan Sadhasivam
167046c6b0SManivannan Sadhasivam  This binding uses common clock bindings
177046c6b0SManivannan Sadhasivam  [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
187046c6b0SManivannan Sadhasivam
197046c6b0SManivannan Sadhasivamproperties:
207046c6b0SManivannan Sadhasivam  compatible:
217046c6b0SManivannan Sadhasivam    const: bitmain,bm1880-clk
227046c6b0SManivannan Sadhasivam
237046c6b0SManivannan Sadhasivam  reg:
247046c6b0SManivannan Sadhasivam    items:
257046c6b0SManivannan Sadhasivam      - description: pll registers
267046c6b0SManivannan Sadhasivam      - description: system registers
277046c6b0SManivannan Sadhasivam
287046c6b0SManivannan Sadhasivam  reg-names:
297046c6b0SManivannan Sadhasivam    items:
307046c6b0SManivannan Sadhasivam      - const: pll
317046c6b0SManivannan Sadhasivam      - const: sys
327046c6b0SManivannan Sadhasivam
337046c6b0SManivannan Sadhasivam  clocks:
347046c6b0SManivannan Sadhasivam    maxItems: 1
357046c6b0SManivannan Sadhasivam
367046c6b0SManivannan Sadhasivam  clock-names:
377046c6b0SManivannan Sadhasivam    const: osc
387046c6b0SManivannan Sadhasivam
397046c6b0SManivannan Sadhasivam  '#clock-cells':
407046c6b0SManivannan Sadhasivam    const: 1
417046c6b0SManivannan Sadhasivam
427046c6b0SManivannan Sadhasivamrequired:
437046c6b0SManivannan Sadhasivam  - compatible
447046c6b0SManivannan Sadhasivam  - reg
457046c6b0SManivannan Sadhasivam  - reg-names
467046c6b0SManivannan Sadhasivam  - clocks
477046c6b0SManivannan Sadhasivam  - clock-names
487046c6b0SManivannan Sadhasivam  - '#clock-cells'
497046c6b0SManivannan Sadhasivam
507046c6b0SManivannan SadhasivamadditionalProperties: false
517046c6b0SManivannan Sadhasivam
527046c6b0SManivannan Sadhasivamexamples:
537046c6b0SManivannan Sadhasivam  # Clock controller node:
547046c6b0SManivannan Sadhasivam  - |
557046c6b0SManivannan Sadhasivam    clk: clock-controller@e8 {
567046c6b0SManivannan Sadhasivam        compatible = "bitmain,bm1880-clk";
577046c6b0SManivannan Sadhasivam        reg = <0xe8 0x0c>, <0x800 0xb0>;
587046c6b0SManivannan Sadhasivam        reg-names = "pll", "sys";
597046c6b0SManivannan Sadhasivam        clocks = <&osc>;
607046c6b0SManivannan Sadhasivam        clock-names = "osc";
617046c6b0SManivannan Sadhasivam        #clock-cells = <1>;
627046c6b0SManivannan Sadhasivam    };
637046c6b0SManivannan Sadhasivam
647046c6b0SManivannan Sadhasivam...
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