xref: /linux/Documentation/devicetree/bindings/clock/amlogic,c3-pll-clkc.yaml (revision 6e7fd890f1d6ac83805409e9c346240de2705584) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2# Copyright (C) 2022-2023 Amlogic, Inc. All rights reserved
3%YAML 1.2
4---
5$id: http://devicetree.org/schemas/clock/amlogic,c3-pll-clkc.yaml#
6$schema: http://devicetree.org/meta-schemas/core.yaml#
7
8title: Amlogic C3 series PLL Clock Controller
9
10maintainers:
11  - Neil Armstrong <neil.armstrong@linaro.org>
12  - Jerome Brunet <jbrunet@baylibre.com>
13  - Chuan Liu <chuan.liu@amlogic.com>
14  - Xianwei Zhao <xianwei.zhao@amlogic.com>
15
16properties:
17  compatible:
18    const: amlogic,c3-pll-clkc
19
20  reg:
21    maxItems: 1
22
23  clocks:
24    items:
25      - description: input top pll
26      - description: input mclk pll
27
28  clock-names:
29    items:
30      - const: top
31      - const: mclk
32
33  "#clock-cells":
34    const: 1
35
36required:
37  - compatible
38  - reg
39  - clocks
40  - clock-names
41  - "#clock-cells"
42
43additionalProperties: false
44
45examples:
46  - |
47    apb {
48        #address-cells = <2>;
49        #size-cells = <2>;
50
51        clock-controller@8000 {
52            compatible = "amlogic,c3-pll-clkc";
53            reg = <0x0 0x8000 0x0 0x1a4>;
54            clocks = <&scmi_clk 2>,
55                     <&scmi_clk 5>;
56            clock-names = "top", "mclk";
57            #clock-cells = <1>;
58        };
59    };
60