xref: /linux/Documentation/devicetree/bindings/clock/amlogic,a1-peripherals-clkc.yaml (revision 42d37fc0c819b81f6f6afd108b55d04ba9d32d0f) 
1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/clock/amlogic,a1-peripherals-clkc.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Amlogic A1 Peripherals Clock Control Unit
8
9maintainers:
10  - Neil Armstrong <neil.armstrong@linaro.org>
11  - Jerome Brunet <jbrunet@baylibre.com>
12  - Jian Hu <jian.hu@jian.hu.com>
13  - Dmitry Rokosov <ddrokosov@sberdevices.ru>
14
15properties:
16  compatible:
17    const: amlogic,a1-peripherals-clkc
18
19  '#clock-cells':
20    const: 1
21
22  reg:
23    maxItems: 1
24
25  clocks:
26    items:
27      - description: input fixed pll div2
28      - description: input fixed pll div3
29      - description: input fixed pll div5
30      - description: input fixed pll div7
31      - description: input hifi pll
32      - description: input oscillator (usually at 24MHz)
33      - description: input sys pll
34    minItems: 6 # sys_pll is optional
35
36  clock-names:
37    items:
38      - const: fclk_div2
39      - const: fclk_div3
40      - const: fclk_div5
41      - const: fclk_div7
42      - const: hifi_pll
43      - const: xtal
44      - const: sys_pll
45    minItems: 6 # sys_pll is optional
46
47required:
48  - compatible
49  - '#clock-cells'
50  - reg
51  - clocks
52  - clock-names
53
54additionalProperties: false
55
56examples:
57  - |
58    #include <dt-bindings/clock/amlogic,a1-pll-clkc.h>
59    apb {
60        #address-cells = <2>;
61        #size-cells = <2>;
62
63        clock-controller@800 {
64            compatible = "amlogic,a1-peripherals-clkc";
65            reg = <0 0x800 0 0x104>;
66            #clock-cells = <1>;
67            clocks = <&clkc_pll CLKID_FCLK_DIV2>,
68                     <&clkc_pll CLKID_FCLK_DIV3>,
69                     <&clkc_pll CLKID_FCLK_DIV5>,
70                     <&clkc_pll CLKID_FCLK_DIV7>,
71                     <&clkc_pll CLKID_HIFI_PLL>,
72                     <&xtal>,
73                     <&clkc_pll CLKID_SYS_PLL>;
74            clock-names = "fclk_div2", "fclk_div3",
75                          "fclk_div5", "fclk_div7",
76                          "hifi_pll", "xtal", "sys_pll";
77        };
78    };
79