1b4156204SJian Hu# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2b4156204SJian Hu# Copyright (C) 2024-2025 Amlogic, Inc. All rights reserved 3b4156204SJian Hu%YAML 1.2 4b4156204SJian Hu--- 5b4156204SJian Hu$id: http://devicetree.org/schemas/clock/amlogic,t7-peripherals-clkc.yaml# 6b4156204SJian Hu$schema: http://devicetree.org/meta-schemas/core.yaml# 7b4156204SJian Hu 8b4156204SJian Hutitle: Amlogic T7 Peripherals Clock Controller 9b4156204SJian Hu 10b4156204SJian Humaintainers: 11b4156204SJian Hu - Neil Armstrong <neil.armstrong@linaro.org> 12b4156204SJian Hu - Jerome Brunet <jbrunet@baylibre.com> 13b4156204SJian Hu - Xianwei Zhao <xianwei.zhao@amlogic.com> 14b4156204SJian Hu - Jian Hu <jian.hu@amlogic.com> 15b4156204SJian Hu 16b4156204SJian Huproperties: 17b4156204SJian Hu compatible: 18b4156204SJian Hu const: amlogic,t7-peripherals-clkc 19b4156204SJian Hu 20b4156204SJian Hu reg: 21b4156204SJian Hu maxItems: 1 22b4156204SJian Hu 23b4156204SJian Hu '#clock-cells': 24b4156204SJian Hu const: 1 25b4156204SJian Hu 26b4156204SJian Hu clocks: 27*ca89c88bSJian Hu minItems: 15 28b4156204SJian Hu items: 29b4156204SJian Hu - description: input oscillator 30b4156204SJian Hu - description: input sys clk 31b4156204SJian Hu - description: input fixed pll 32b4156204SJian Hu - description: input fclk div 2 33b4156204SJian Hu - description: input fclk div 2p5 34b4156204SJian Hu - description: input fclk div 3 35b4156204SJian Hu - description: input fclk div 4 36b4156204SJian Hu - description: input fclk div 5 37b4156204SJian Hu - description: input fclk div 7 38b4156204SJian Hu - description: input hifi pll 39b4156204SJian Hu - description: input gp0 pll 40b4156204SJian Hu - description: input gp1 pll 41b4156204SJian Hu - description: input mpll1 42b4156204SJian Hu - description: input mpll2 43*ca89c88bSJian Hu - description: input mpll3 44b4156204SJian Hu - description: external input rmii oscillator (optional) 45b4156204SJian Hu - description: input video pll0 (optional) 46b4156204SJian Hu - description: external pad input for rtc (optional) 47b4156204SJian Hu 48b4156204SJian Hu clock-names: 49*ca89c88bSJian Hu minItems: 15 50b4156204SJian Hu items: 51b4156204SJian Hu - const: xtal 52b4156204SJian Hu - const: sys 53b4156204SJian Hu - const: fix 54b4156204SJian Hu - const: fdiv2 55b4156204SJian Hu - const: fdiv2p5 56b4156204SJian Hu - const: fdiv3 57b4156204SJian Hu - const: fdiv4 58b4156204SJian Hu - const: fdiv5 59b4156204SJian Hu - const: fdiv7 60b4156204SJian Hu - const: hifi 61b4156204SJian Hu - const: gp0 62b4156204SJian Hu - const: gp1 63b4156204SJian Hu - const: mpll1 64b4156204SJian Hu - const: mpll2 65*ca89c88bSJian Hu - const: mpll3 66b4156204SJian Hu - const: ext_rmii 67b4156204SJian Hu - const: vid_pll0 68b4156204SJian Hu - const: ext_rtc 69b4156204SJian Hu 70b4156204SJian Hurequired: 71b4156204SJian Hu - compatible 72b4156204SJian Hu - '#clock-cells' 73b4156204SJian Hu - reg 74b4156204SJian Hu - clocks 75b4156204SJian Hu - clock-names 76b4156204SJian Hu 77b4156204SJian HuadditionalProperties: false 78b4156204SJian Hu 79b4156204SJian Huexamples: 80b4156204SJian Hu - | 81b4156204SJian Hu apb { 82b4156204SJian Hu #address-cells = <2>; 83b4156204SJian Hu #size-cells = <2>; 84b4156204SJian Hu 85b4156204SJian Hu clkc_periphs:clock-controller@0 { 86b4156204SJian Hu compatible = "amlogic,t7-peripherals-clkc"; 87b4156204SJian Hu reg = <0 0x0 0 0x1c8>; 88b4156204SJian Hu #clock-cells = <1>; 89b4156204SJian Hu clocks = <&xtal>, 90b4156204SJian Hu <&scmi_clk 13>, 91b4156204SJian Hu <&scmi_clk 16>, 92b4156204SJian Hu <&scmi_clk 18>, 93b4156204SJian Hu <&scmi_clk 20>, 94b4156204SJian Hu <&scmi_clk 22>, 95b4156204SJian Hu <&scmi_clk 24>, 96b4156204SJian Hu <&scmi_clk 26>, 97b4156204SJian Hu <&scmi_clk 28>, 98b4156204SJian Hu <&hifi 1>, 99b4156204SJian Hu <&gp0 1>, 100b4156204SJian Hu <&gp1 1>, 101b4156204SJian Hu <&mpll 4>, 102*ca89c88bSJian Hu <&mpll 6>, 103*ca89c88bSJian Hu <&mpll 8>; 104b4156204SJian Hu clock-names = "xtal", 105b4156204SJian Hu "sys", 106b4156204SJian Hu "fix", 107b4156204SJian Hu "fdiv2", 108b4156204SJian Hu "fdiv2p5", 109b4156204SJian Hu "fdiv3", 110b4156204SJian Hu "fdiv4", 111b4156204SJian Hu "fdiv5", 112b4156204SJian Hu "fdiv7", 113b4156204SJian Hu "hifi", 114b4156204SJian Hu "gp0", 115b4156204SJian Hu "gp1", 116b4156204SJian Hu "mpll1", 117*ca89c88bSJian Hu "mpll2", 118*ca89c88bSJian Hu "mpll3"; 119b4156204SJian Hu }; 120b4156204SJian Hu }; 121