1*d4255960SJian Hu# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*d4255960SJian Hu# Copyright (C) 2026 Amlogic, Inc. All rights reserved 3*d4255960SJian Hu%YAML 1.2 4*d4255960SJian Hu--- 5*d4255960SJian Hu$id: http://devicetree.org/schemas/clock/amlogic,a9-aoclkc.yaml# 6*d4255960SJian Hu$schema: http://devicetree.org/meta-schemas/core.yaml# 7*d4255960SJian Hu 8*d4255960SJian Hutitle: Amlogic A9 Series Always-On Clock Controller 9*d4255960SJian Hu 10*d4255960SJian Humaintainers: 11*d4255960SJian Hu - Neil Armstrong <neil.armstrong@linaro.org> 12*d4255960SJian Hu - Jerome Brunet <jbrunet@baylibre.com> 13*d4255960SJian Hu - Jian Hu <jian.hu@amlogic.com> 14*d4255960SJian Hu - Xianwei Zhao <xianwei.zhao@amlogic.com> 15*d4255960SJian Hu 16*d4255960SJian Huproperties: 17*d4255960SJian Hu compatible: 18*d4255960SJian Hu const: amlogic,a9-aoclkc 19*d4255960SJian Hu 20*d4255960SJian Hu reg: 21*d4255960SJian Hu maxItems: 1 22*d4255960SJian Hu 23*d4255960SJian Hu '#clock-cells': 24*d4255960SJian Hu const: 1 25*d4255960SJian Hu 26*d4255960SJian Hu clocks: 27*d4255960SJian Hu minItems: 5 28*d4255960SJian Hu items: 29*d4255960SJian Hu - description: input oscillator 30*d4255960SJian Hu - description: input fclk div 3 31*d4255960SJian Hu - description: input fclk div 4 32*d4255960SJian Hu - description: input fclk div 5 33*d4255960SJian Hu - description: input sys clk 34*d4255960SJian Hu - description: external fixed 32k (optional) 35*d4255960SJian Hu 36*d4255960SJian Hu clock-names: 37*d4255960SJian Hu minItems: 5 38*d4255960SJian Hu items: 39*d4255960SJian Hu - const: xtal 40*d4255960SJian Hu - const: fdiv3 41*d4255960SJian Hu - const: fdiv4 42*d4255960SJian Hu - const: fdiv5 43*d4255960SJian Hu - const: sys 44*d4255960SJian Hu - const: ext_32k 45*d4255960SJian Hu 46*d4255960SJian Hurequired: 47*d4255960SJian Hu - compatible 48*d4255960SJian Hu - reg 49*d4255960SJian Hu - '#clock-cells' 50*d4255960SJian Hu - clocks 51*d4255960SJian Hu - clock-names 52*d4255960SJian Hu 53*d4255960SJian HuadditionalProperties: false 54*d4255960SJian Hu 55*d4255960SJian Huexamples: 56*d4255960SJian Hu - | 57*d4255960SJian Hu soc { 58*d4255960SJian Hu #address-cells = <2>; 59*d4255960SJian Hu #size-cells = <2>; 60*d4255960SJian Hu 61*d4255960SJian Hu clock-controller@0 { 62*d4255960SJian Hu compatible = "amlogic,a9-aoclkc"; 63*d4255960SJian Hu reg = <0x0 0x0 0x0 0x58>; 64*d4255960SJian Hu #clock-cells = <1>; 65*d4255960SJian Hu clocks = <&xtal>, 66*d4255960SJian Hu <&scmi_clk 14>, 67*d4255960SJian Hu <&scmi_clk 16>, 68*d4255960SJian Hu <&scmi_clk 18>, 69*d4255960SJian Hu <&scmi_clk 21>; 70*d4255960SJian Hu clock-names = "xtal", 71*d4255960SJian Hu "fdiv3", 72*d4255960SJian Hu "fdiv4", 73*d4255960SJian Hu "fdiv5", 74*d4255960SJian Hu "sys"; 75*d4255960SJian Hu }; 76*d4255960SJian Hu }; 77