xref: /linux/Documentation/devicetree/bindings/clock/adi,axi-clkgen.yaml (revision 842ed298954db7dc41a4942f3331d19cd9676ede) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/clock/adi,axi-clkgen.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Binding for Analog Devices AXI clkgen pcore clock generator
8
9maintainers:
10  - Lars-Peter Clausen <lars@metafoo.de>
11  - Michael Hennerich <michael.hennerich@analog.com>
12
13description: |
14  The axi_clkgen IP core is a software programmable clock generator,
15  that can be synthesized on various FPGA platforms.
16
17  Link: https://wiki.analog.com/resources/fpga/docs/axi_clkgen
18
19properties:
20  compatible:
21    enum:
22      - adi,axi-clkgen-2.00.a
23
24  clocks:
25    description:
26      Specifies the reference clock(s) from which the output frequency is
27      derived. This must either reference one clock if only the first clock
28      input is connected or two if both clock inputs are connected.
29    minItems: 1
30    maxItems: 2
31
32  '#clock-cells':
33    const: 0
34
35  reg:
36    maxItems: 1
37
38required:
39  - compatible
40  - reg
41  - clocks
42  - '#clock-cells'
43
44additionalProperties: false
45
46examples:
47  - |
48    clock-controller@ff000000 {
49      compatible = "adi,axi-clkgen-2.00.a";
50      #clock-cells = <0>;
51      reg = <0xff000000 0x1000>;
52      clocks = <&osc 1>;
53    };
54