1# SPDX-License-Identifier: GPL-2.0 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/cache/l2c2x0.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: ARM L2 Cache Controller 8 9maintainers: 10 - Rob Herring <robh@kernel.org> 11 12description: |+ 13 ARM cores often have a separate L2C210/L2C220/L2C310 (also known as PL210/ 14 PL220/PL310 and variants) based level 2 cache controller. All these various 15 implementations of the L2 cache controller have compatible programming 16 models (Note 1). Some of the properties that are just prefixed "cache-*" are 17 taken from section 3.7.3 of the Devicetree Specification which can be found 18 at: 19 https://www.devicetree.org/specifications/ 20 21 Note 1: The description in this document doesn't apply to integrated L2 22 cache controllers as found in e.g. Cortex-A15/A7/A57/A53. These 23 integrated L2 controllers are assumed to be all preconfigured by 24 early secure boot code. Thus no need to deal with their configuration 25 in the kernel at all. 26 27allOf: 28 - $ref: /schemas/cache-controller.yaml# 29 30properties: 31 compatible: 32 oneOf: 33 - enum: 34 - arm,pl310-cache 35 - arm,l220-cache 36 - arm,l210-cache 37 # DEPRECATED by "brcm,bcm11351-a2-pl310-cache" 38 - bcm,bcm11351-a2-pl310-cache 39 # For Broadcom bcm11351 chipset where an 40 # offset needs to be added to the address before passing down to the L2 41 # cache controller 42 - brcm,bcm11351-a2-pl310-cache 43 # Marvell Controller designed to be 44 # compatible with the ARM one, with system cache mode (meaning 45 # maintenance operations on L1 are broadcasted to the L2 and L2 46 # performs the same operation). 47 - marvell,aurora-system-cache 48 # Marvell Controller designed to be 49 # compatible with the ARM one with outer cache mode. 50 - marvell,aurora-outer-cache 51 - items: 52 # Marvell Tauros3 cache controller, compatible 53 # with arm,pl310-cache controller. 54 - const: marvell,tauros3-cache 55 - const: arm,pl310-cache 56 57 cache-level: 58 const: 2 59 60 cache-unified: true 61 cache-size: true 62 cache-sets: true 63 cache-block-size: true 64 cache-line-size: true 65 66 reg: 67 maxItems: 1 68 69 power-domains: 70 maxItems: 1 71 72 arm,data-latency: 73 description: Cycles of latency for Data RAM accesses. Specifies 3 cells of 74 read, write and setup latencies. Minimum valid values are 1. Controllers 75 without setup latency control should use a value of 0. 76 $ref: /schemas/types.yaml#/definitions/uint32-array 77 minItems: 2 78 maxItems: 3 79 items: 80 minimum: 0 81 maximum: 8 82 83 arm,tag-latency: 84 description: Cycles of latency for Tag RAM accesses. Specifies 3 cells of 85 read, write and setup latencies. Controllers without setup latency control 86 should use 0. Controllers without separate read and write Tag RAM latency 87 values should only use the first cell. 88 $ref: /schemas/types.yaml#/definitions/uint32-array 89 minItems: 1 90 maxItems: 3 91 items: 92 minimum: 0 93 maximum: 8 94 95 arm,dirty-latency: 96 description: Cycles of latency for Dirty RAMs. This is a single cell. 97 $ref: /schemas/types.yaml#/definitions/uint32 98 minimum: 1 99 maximum: 8 100 101 arm,filter-ranges: 102 description: <start length> Starting address and length of window to 103 filter. Addresses in the filter window are directed to the M1 port. Other 104 addresses will go to the M0 port. 105 $ref: /schemas/types.yaml#/definitions/uint32-array 106 minItems: 2 107 maxItems: 2 108 109 arm,io-coherent: 110 description: indicates that the system is operating in an hardware 111 I/O coherent mode. Valid only when the arm,pl310-cache compatible 112 string is used. 113 type: boolean 114 115 interrupts: 116 # Either a single combined interrupt or up to 9 individual interrupts 117 minItems: 1 118 maxItems: 9 119 120 cache-id-part: 121 description: cache id part number to be used if it is not present 122 on hardware 123 $ref: /schemas/types.yaml#/definitions/uint32 124 125 wt-override: 126 description: If present then L2 is forced to Write through mode 127 type: boolean 128 129 arm,double-linefill: 130 description: Override double linefill enable setting. Enable if 131 non-zero, disable if zero. 132 $ref: /schemas/types.yaml#/definitions/uint32 133 enum: [0, 1] 134 135 arm,double-linefill-incr: 136 description: Override double linefill on INCR read. Enable 137 if non-zero, disable if zero. 138 $ref: /schemas/types.yaml#/definitions/uint32 139 enum: [0, 1] 140 141 arm,double-linefill-wrap: 142 description: Override double linefill on WRAP read. Enable 143 if non-zero, disable if zero. 144 $ref: /schemas/types.yaml#/definitions/uint32 145 enum: [0, 1] 146 147 arm,prefetch-drop: 148 description: Override prefetch drop enable setting. Enable if non-zero, 149 disable if zero. 150 $ref: /schemas/types.yaml#/definitions/uint32 151 enum: [0, 1] 152 153 arm,prefetch-offset: 154 description: Override prefetch offset value. 155 $ref: /schemas/types.yaml#/definitions/uint32 156 enum: [0, 1, 2, 3, 4, 5, 6, 7, 15, 23, 31] 157 158 arm,shared-override: 159 description: The default behavior of the L220 or PL310 cache 160 controllers with respect to the shareable attribute is to transform "normal 161 memory non-cacheable transactions" into "cacheable no allocate" (for reads) 162 or "write through no write allocate" (for writes). 163 On systems where this may cause DMA buffer corruption, this property must 164 be specified to indicate that such transforms are precluded. 165 type: boolean 166 167 arm,parity-enable: 168 description: enable parity checking on the L2 cache (L220 or PL310). 169 type: boolean 170 171 arm,parity-disable: 172 description: disable parity checking on the L2 cache (L220 or PL310). 173 type: boolean 174 175 marvell,ecc-enable: 176 description: enable ECC protection on the L2 cache 177 type: boolean 178 179 arm,outer-sync-disable: 180 description: disable the outer sync operation on the L2 cache. 181 Some core tiles, especially ARM PB11MPCore have a faulty L220 cache that 182 will randomly hang unless outer sync operations are disabled. 183 type: boolean 184 185 prefetch-data: 186 description: | 187 Data prefetch. Value: <0> (forcibly disable), <1> 188 (forcibly enable), property absent (retain settings set by firmware) 189 $ref: /schemas/types.yaml#/definitions/uint32 190 enum: [0, 1] 191 192 prefetch-instr: 193 description: | 194 Instruction prefetch. Value: <0> (forcibly disable), 195 <1> (forcibly enable), property absent (retain settings set by 196 firmware) 197 $ref: /schemas/types.yaml#/definitions/uint32 198 enum: [0, 1] 199 200 arm,dynamic-clock-gating: 201 description: | 202 L2 dynamic clock gating. Value: <0> (forcibly 203 disable), <1> (forcibly enable), property absent (OS specific behavior, 204 preferably retain firmware settings) 205 $ref: /schemas/types.yaml#/definitions/uint32 206 enum: [0, 1] 207 208 arm,standby-mode: 209 description: L2 standby mode enable. Value <0> (forcibly disable), 210 <1> (forcibly enable), property absent (OS specific behavior, 211 preferably retain firmware settings) 212 $ref: /schemas/types.yaml#/definitions/uint32 213 enum: [0, 1] 214 215 arm,early-bresp-disable: 216 description: Disable the CA9 optimization Early BRESP (PL310) 217 type: boolean 218 219 arm,full-line-zero-disable: 220 description: Disable the CA9 optimization Full line of zero 221 write (PL310) 222 type: boolean 223 224required: 225 - compatible 226 - cache-unified 227 - reg 228 229additionalProperties: false 230 231examples: 232 - | 233 cache-controller@fff12000 { 234 compatible = "arm,pl310-cache"; 235 reg = <0xfff12000 0x1000>; 236 arm,data-latency = <1 1 1>; 237 arm,tag-latency = <2 2 2>; 238 arm,filter-ranges = <0x80000000 0x8000000>; 239 cache-unified; 240 cache-level = <2>; 241 interrupts = <45>; 242 }; 243 244... 245