xref: /linux/Documentation/devicetree/bindings/bus/qcom,ssc-block-bus.yaml (revision da1d9caf95def6f0320819cf941c9fd1069ba9e1) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/bus/qcom,ssc-block-bus.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: The AHB Bus Providing a Global View of the SSC Block on (some) qcom SoCs
8
9maintainers:
10  - Michael Srba <Michael.Srba@seznam.cz>
11
12description: |
13  This binding describes the dependencies (clocks, resets, power domains) which
14  need to be turned on in a sequence before communication over the AHB bus
15  becomes possible.
16
17  Additionally, the reg property is used to pass to the driver the location of
18  two sadly undocumented registers which need to be poked as part of the sequence.
19
20  The SSC (Snapdragon Sensor Core) block contains a gpio controller, i2c/spi/uart
21  controllers, a hexagon core, and a clock controller which provides clocks for
22  the above.
23
24properties:
25  compatible:
26    items:
27      - const: qcom,msm8998-ssc-block-bus
28      - const: qcom,ssc-block-bus
29
30  reg:
31    description: |
32      Shall contain the addresses of the SSCAON_CONFIG0 and SSCAON_CONFIG1
33      registers
34    minItems: 2
35    maxItems: 2
36
37  reg-names:
38    items:
39      - const: mpm_sscaon_config0
40      - const: mpm_sscaon_config1
41
42  '#address-cells':
43    enum: [ 1, 2 ]
44
45  '#size-cells':
46    enum: [ 1, 2 ]
47
48  ranges: true
49
50  clocks:
51    minItems: 6
52    maxItems: 6
53
54  clock-names:
55    items:
56      - const: xo
57      - const: aggre2
58      - const: gcc_im_sleep
59      - const: aggre2_north
60      - const: ssc_xo
61      - const: ssc_ahbs
62
63  power-domains:
64    description: Power domain phandles for the ssc_cx and ssc_mx power domains
65    minItems: 2
66    maxItems: 2
67
68  power-domain-names:
69    items:
70      - const: ssc_cx
71      - const: ssc_mx
72
73  resets:
74    description: |
75      Reset phandles for the ssc_reset and ssc_bcr resets (note: ssc_bcr is the
76      branch control register associated with the ssc_xo and ssc_ahbs clocks)
77    minItems: 2
78    maxItems: 2
79
80  reset-names:
81    items:
82      - const: ssc_reset
83      - const: ssc_bcr
84
85  qcom,halt-regs:
86    $ref: /schemas/types.yaml#/definitions/phandle-array
87    description: describes how to locate the ssc AXI halt register
88    items:
89      - items:
90          - description: Phandle reference to a syscon representing TCSR
91          - description: offset for the ssc AXI halt register
92
93required:
94  - compatible
95  - reg
96  - reg-names
97  - '#address-cells'
98  - '#size-cells'
99  - ranges
100  - clocks
101  - clock-names
102  - power-domains
103  - power-domain-names
104  - resets
105  - reset-names
106  - qcom,halt-regs
107
108additionalProperties:
109  type: object
110
111examples:
112  - |
113    #include <dt-bindings/clock/qcom,gcc-msm8998.h>
114    #include <dt-bindings/clock/qcom,rpmcc.h>
115    #include <dt-bindings/power/qcom-rpmpd.h>
116
117    soc {
118        #address-cells = <1>;
119        #size-cells = <1>;
120
121        // devices under this node are physically located in the SSC block, connected to an ssc-internal bus;
122        ssc_ahb_slave: bus@10ac008 {
123            #address-cells = <1>;
124            #size-cells = <1>;
125            ranges;
126
127            compatible = "qcom,msm8998-ssc-block-bus", "qcom,ssc-block-bus";
128            reg = <0x10ac008 0x4>, <0x10ac010 0x4>;
129            reg-names = "mpm_sscaon_config0", "mpm_sscaon_config1";
130
131            clocks = <&xo>,
132                     <&rpmcc RPM_SMD_AGGR2_NOC_CLK>,
133                     <&gcc GCC_IM_SLEEP>,
134                     <&gcc AGGRE2_SNOC_NORTH_AXI>,
135                     <&gcc SSC_XO>,
136                     <&gcc SSC_CNOC_AHBS_CLK>;
137            clock-names = "xo", "aggre2", "gcc_im_sleep", "aggre2_north", "ssc_xo", "ssc_ahbs";
138
139            resets = <&gcc GCC_SSC_RESET>, <&gcc GCC_SSC_BCR>;
140            reset-names = "ssc_reset", "ssc_bcr";
141
142            power-domains = <&rpmpd MSM8998_SSCCX>, <&rpmpd MSM8998_SSCMX>;
143            power-domain-names = "ssc_cx", "ssc_mx";
144
145            qcom,halt-regs = <&tcsr_mutex_regs 0x26000>;
146        };
147    };
148