xref: /linux/Documentation/devicetree/bindings/bus/qcom,ssc-block-bus.yaml (revision c532de5a67a70f8533d495f8f2aaa9a0491c3ad0) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/bus/qcom,ssc-block-bus.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: The AHB Bus Providing a Global View of the SSC Block on (some) qcom SoCs
8
9maintainers:
10  - Michael Srba <Michael.Srba@seznam.cz>
11
12description: |
13  This binding describes the dependencies (clocks, resets, power domains) which
14  need to be turned on in a sequence before communication over the AHB bus
15  becomes possible.
16
17  Additionally, the reg property is used to pass to the driver the location of
18  two sadly undocumented registers which need to be poked as part of the sequence.
19
20  The SSC (Snapdragon Sensor Core) block contains a gpio controller, i2c/spi/uart
21  controllers, a hexagon core, and a clock controller which provides clocks for
22  the above.
23
24properties:
25  compatible:
26    items:
27      - const: qcom,msm8998-ssc-block-bus
28      - const: qcom,ssc-block-bus
29
30  reg:
31    items:
32      - description: SSCAON_CONFIG0 registers
33      - description: SSCAON_CONFIG1 registers
34
35  reg-names:
36    items:
37      - const: mpm_sscaon_config0
38      - const: mpm_sscaon_config1
39
40  '#address-cells':
41    enum: [ 1, 2 ]
42
43  '#size-cells':
44    enum: [ 1, 2 ]
45
46  ranges: true
47
48  clocks:
49    maxItems: 6
50
51  clock-names:
52    items:
53      - const: xo
54      - const: aggre2
55      - const: gcc_im_sleep
56      - const: aggre2_north
57      - const: ssc_xo
58      - const: ssc_ahbs
59
60  power-domains:
61    items:
62      - description: CX power domain
63      - description: MX power domain
64
65  power-domain-names:
66    items:
67      - const: ssc_cx
68      - const: ssc_mx
69
70  resets:
71    items:
72      - description: Main reset
73      - description:
74          SSC Branch Control Register reset (associated with the ssc_xo and
75          ssc_ahbs clocks)
76
77  reset-names:
78    items:
79      - const: ssc_reset
80      - const: ssc_bcr
81
82  qcom,halt-regs:
83    $ref: /schemas/types.yaml#/definitions/phandle-array
84    description: describes how to locate the ssc AXI halt register
85    items:
86      - items:
87          - description: Phandle reference to a syscon representing TCSR
88          - description: offset for the ssc AXI halt register
89
90required:
91  - compatible
92  - reg
93  - reg-names
94  - '#address-cells'
95  - '#size-cells'
96  - ranges
97  - clocks
98  - clock-names
99  - power-domains
100  - power-domain-names
101  - resets
102  - reset-names
103  - qcom,halt-regs
104
105additionalProperties:
106  type: object
107
108examples:
109  - |
110    #include <dt-bindings/clock/qcom,gcc-msm8998.h>
111    #include <dt-bindings/clock/qcom,rpmcc.h>
112    #include <dt-bindings/power/qcom-rpmpd.h>
113
114    soc {
115        #address-cells = <1>;
116        #size-cells = <1>;
117
118        // devices under this node are physically located in the SSC block, connected to an ssc-internal bus;
119        ssc_ahb_slave: bus@10ac008 {
120            #address-cells = <1>;
121            #size-cells = <1>;
122            ranges;
123
124            compatible = "qcom,msm8998-ssc-block-bus", "qcom,ssc-block-bus";
125            reg = <0x10ac008 0x4>, <0x10ac010 0x4>;
126            reg-names = "mpm_sscaon_config0", "mpm_sscaon_config1";
127
128            clocks = <&xo>,
129                     <&rpmcc RPM_SMD_AGGR2_NOC_CLK>,
130                     <&gcc GCC_IM_SLEEP>,
131                     <&gcc AGGRE2_SNOC_NORTH_AXI>,
132                     <&gcc SSC_XO>,
133                     <&gcc SSC_CNOC_AHBS_CLK>;
134            clock-names = "xo", "aggre2", "gcc_im_sleep", "aggre2_north", "ssc_xo", "ssc_ahbs";
135
136            resets = <&gcc GCC_SSC_RESET>, <&gcc GCC_SSC_BCR>;
137            reset-names = "ssc_reset", "ssc_bcr";
138
139            power-domains = <&rpmpd MSM8998_SSCCX>, <&rpmpd MSM8998_SSCMX>;
140            power-domain-names = "ssc_cx", "ssc_mx";
141
142            qcom,halt-regs = <&tcsr_mutex_regs 0x26000>;
143        };
144    };
145