xref: /linux/Documentation/devicetree/bindings/ata/snps,dwc-ahci.yaml (revision c532de5a67a70f8533d495f8f2aaa9a0491c3ad0) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/ata/snps,dwc-ahci.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Synopsys DWC AHCI SATA controller
8
9maintainers:
10  - Serge Semin <fancer.lancer@gmail.com>
11
12description:
13  This document defines device tree bindings for the generic Synopsys DWC
14  implementation of the AHCI SATA controller.
15
16select:
17  properties:
18    compatible:
19      enum:
20        - snps,dwc-ahci
21        - snps,spear-ahci
22  required:
23    - compatible
24
25allOf:
26  - $ref: snps,dwc-ahci-common.yaml#
27
28properties:
29  compatible:
30    oneOf:
31      - description: Synopsys AHCI SATA-compatible devices
32        const: snps,dwc-ahci
33      - description: SPEAr1340 AHCI SATA device
34        const: snps,spear-ahci
35
36patternProperties:
37  "^sata-port@[0-9a-e]$":
38    $ref: /schemas/ata/snps,dwc-ahci-common.yaml#/$defs/dwc-ahci-port
39
40    unevaluatedProperties: false
41
42required:
43  - compatible
44  - reg
45  - interrupts
46
47unevaluatedProperties: false
48
49examples:
50  - |
51    #include <dt-bindings/interrupt-controller/arm-gic.h>
52    #include <dt-bindings/ata/ahci.h>
53
54    sata@122f0000 {
55      compatible = "snps,dwc-ahci";
56      reg = <0x122F0000 0x1ff>;
57      #address-cells = <1>;
58      #size-cells = <0>;
59
60      interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
61
62      clocks = <&clock1>, <&clock2>;
63      clock-names = "aclk", "ref";
64
65      phys = <&sata_phy>;
66      phy-names = "sata-phy";
67
68      ports-implemented = <0x1>;
69
70      sata-port@0 {
71        reg = <0>;
72
73        hba-port-cap = <HBA_PORT_FBSCP>;
74
75        snps,tx-ts-max = <512>;
76        snps,rx-ts-max = <512>;
77      };
78    };
79
80...
81