xref: /linux/Documentation/devicetree/bindings/ata/snps,dwc-ahci.yaml (revision 4078aa68509746d0c1a70c50ab22a761ad7c2e0d) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/ata/snps,dwc-ahci.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Synopsys DWC AHCI SATA controller
8
9maintainers:
10  - Serge Semin <fancer.lancer@gmail.com>
11
12description:
13  This document defines device tree bindings for the generic Synopsys DWC
14  implementation of the AHCI SATA controller.
15
16allOf:
17  - $ref: snps,dwc-ahci-common.yaml#
18
19properties:
20  compatible:
21    oneOf:
22      - description: Synopsys AHCI SATA-compatible devices
23        const: snps,dwc-ahci
24      - description: SPEAr1340 AHCI SATA device
25        const: snps,spear-ahci
26      - description: Rockhip RK3568 AHCI controller
27        items:
28          - const: rockchip,rk3568-dwc-ahci
29          - const: snps,dwc-ahci
30
31patternProperties:
32  "^sata-port@[0-9a-e]$":
33    $ref: /schemas/ata/snps,dwc-ahci-common.yaml#/$defs/dwc-ahci-port
34
35    unevaluatedProperties: false
36
37required:
38  - compatible
39  - reg
40  - interrupts
41
42unevaluatedProperties: false
43
44examples:
45  - |
46    #include <dt-bindings/interrupt-controller/arm-gic.h>
47    #include <dt-bindings/ata/ahci.h>
48
49    sata@122f0000 {
50      compatible = "snps,dwc-ahci";
51      reg = <0x122F0000 0x1ff>;
52      #address-cells = <1>;
53      #size-cells = <0>;
54
55      interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
56
57      clocks = <&clock1>, <&clock2>;
58      clock-names = "aclk", "ref";
59
60      phys = <&sata_phy>;
61      phy-names = "sata-phy";
62
63      ports-implemented = <0x1>;
64
65      sata-port@0 {
66        reg = <0>;
67
68        hba-port-cap = <HBA_PORT_FBSCP>;
69
70        snps,tx-ts-max = <512>;
71        snps,rx-ts-max = <512>;
72      };
73    };
74
75...
76