1b873c122SLinus Walleij# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2b873c122SLinus Walleij%YAML 1.2 3b873c122SLinus Walleij--- 4b873c122SLinus Walleij$id: http://devicetree.org/schemas/ata/faraday,ftide010.yaml# 5b873c122SLinus Walleij$schema: http://devicetree.org/meta-schemas/core.yaml# 6b873c122SLinus Walleij 7b873c122SLinus Walleijtitle: Faraday Technology FTIDE010 PATA controller 8b873c122SLinus Walleij 9b873c122SLinus Walleijmaintainers: 10b873c122SLinus Walleij - Linus Walleij <linus.walleij@linaro.org> 11b873c122SLinus Walleij 12b873c122SLinus Walleijdescription: | 13b873c122SLinus Walleij This controller is the first Faraday IDE interface block, used in the 14b873c122SLinus Walleij StorLink SL3512 and SL3516, later known as the Cortina Systems Gemini 15b873c122SLinus Walleij platform. The controller can do PIO modes 0 through 4, Multi-word DMA 16b873c122SLinus Walleij (MWDM) modes 0 through 2 and Ultra DMA modes 0 through 6. 17b873c122SLinus Walleij 18b873c122SLinus Walleij On the Gemini platform, this PATA block is accompanied by a PATA to 19b873c122SLinus Walleij SATA bridge in order to support SATA. This is why a phandle to that 20b873c122SLinus Walleij controller is compulsory on that platform. 21b873c122SLinus Walleij 22b873c122SLinus Walleij The timing properties are unique per-SoC, not per-board. 23b873c122SLinus Walleij 24b873c122SLinus Walleijproperties: 25b873c122SLinus Walleij compatible: 26b873c122SLinus Walleij oneOf: 27b873c122SLinus Walleij - const: faraday,ftide010 28b873c122SLinus Walleij - items: 29b873c122SLinus Walleij - const: cortina,gemini-pata 30b873c122SLinus Walleij - const: faraday,ftide010 31b873c122SLinus Walleij 32b873c122SLinus Walleij reg: 33b873c122SLinus Walleij maxItems: 1 34b873c122SLinus Walleij 35b873c122SLinus Walleij interrupts: 36b873c122SLinus Walleij maxItems: 1 37b873c122SLinus Walleij 38b873c122SLinus Walleij clocks: 39b873c122SLinus Walleij minItems: 1 40b873c122SLinus Walleij 41b873c122SLinus Walleij clock-names: 42b873c122SLinus Walleij const: PCLK 43b873c122SLinus Walleij 44b873c122SLinus Walleij sata: 45b873c122SLinus Walleij description: 46b873c122SLinus Walleij phandle to the Gemini PATA to SATA bridge, if available 47b873c122SLinus Walleij $ref: /schemas/types.yaml#/definitions/phandle 48b873c122SLinus Walleij 49b873c122SLinus Walleijrequired: 50b873c122SLinus Walleij - compatible 51b873c122SLinus Walleij - reg 52b873c122SLinus Walleij - interrupts 53b873c122SLinus Walleij 54b873c122SLinus WalleijallOf: 55b873c122SLinus Walleij - $ref: pata-common.yaml# 56b873c122SLinus Walleij 57b873c122SLinus Walleij - if: 58b873c122SLinus Walleij properties: 59b873c122SLinus Walleij compatible: 60b873c122SLinus Walleij contains: 61b873c122SLinus Walleij const: cortina,gemini-pata 62b873c122SLinus Walleij 63b873c122SLinus Walleij then: 64b873c122SLinus Walleij required: 65b873c122SLinus Walleij - sata 66b873c122SLinus Walleij 67*6fdc6e23SRob HerringunevaluatedProperties: false 68*6fdc6e23SRob Herring 69b873c122SLinus Walleijexamples: 70b873c122SLinus Walleij - | 71b873c122SLinus Walleij #include <dt-bindings/interrupt-controller/irq.h> 72b873c122SLinus Walleij #include <dt-bindings/clock/cortina,gemini-clock.h> 73b873c122SLinus Walleij 74b873c122SLinus Walleij ide@63000000 { 75b873c122SLinus Walleij compatible = "cortina,gemini-pata", "faraday,ftide010"; 76b873c122SLinus Walleij reg = <0x63000000 0x100>; 77b873c122SLinus Walleij interrupts = <4 IRQ_TYPE_EDGE_RISING>; 78b873c122SLinus Walleij clocks = <&gcc GEMINI_CLK_GATE_IDE>; 79b873c122SLinus Walleij clock-names = "PCLK"; 80b873c122SLinus Walleij sata = <&sata>; 81b873c122SLinus Walleij #address-cells = <1>; 82b873c122SLinus Walleij #size-cells = <0>; 83b873c122SLinus Walleij ide-port@0 { 84b873c122SLinus Walleij reg = <0>; 85b873c122SLinus Walleij }; 86b873c122SLinus Walleij ide-port@1 { 87b873c122SLinus Walleij reg = <1>; 88b873c122SLinus Walleij }; 89b873c122SLinus Walleij }; 90b873c122SLinus Walleij 91b873c122SLinus Walleij... 92