1*b873c122SLinus Walleij# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*b873c122SLinus Walleij%YAML 1.2 3*b873c122SLinus Walleij--- 4*b873c122SLinus Walleij$id: http://devicetree.org/schemas/ata/faraday,ftide010.yaml# 5*b873c122SLinus Walleij$schema: http://devicetree.org/meta-schemas/core.yaml# 6*b873c122SLinus Walleij 7*b873c122SLinus Walleijtitle: Faraday Technology FTIDE010 PATA controller 8*b873c122SLinus Walleij 9*b873c122SLinus Walleijmaintainers: 10*b873c122SLinus Walleij - Linus Walleij <linus.walleij@linaro.org> 11*b873c122SLinus Walleij 12*b873c122SLinus Walleijdescription: | 13*b873c122SLinus Walleij This controller is the first Faraday IDE interface block, used in the 14*b873c122SLinus Walleij StorLink SL3512 and SL3516, later known as the Cortina Systems Gemini 15*b873c122SLinus Walleij platform. The controller can do PIO modes 0 through 4, Multi-word DMA 16*b873c122SLinus Walleij (MWDM) modes 0 through 2 and Ultra DMA modes 0 through 6. 17*b873c122SLinus Walleij 18*b873c122SLinus Walleij On the Gemini platform, this PATA block is accompanied by a PATA to 19*b873c122SLinus Walleij SATA bridge in order to support SATA. This is why a phandle to that 20*b873c122SLinus Walleij controller is compulsory on that platform. 21*b873c122SLinus Walleij 22*b873c122SLinus Walleij The timing properties are unique per-SoC, not per-board. 23*b873c122SLinus Walleij 24*b873c122SLinus Walleijproperties: 25*b873c122SLinus Walleij compatible: 26*b873c122SLinus Walleij oneOf: 27*b873c122SLinus Walleij - const: faraday,ftide010 28*b873c122SLinus Walleij - items: 29*b873c122SLinus Walleij - const: cortina,gemini-pata 30*b873c122SLinus Walleij - const: faraday,ftide010 31*b873c122SLinus Walleij 32*b873c122SLinus Walleij reg: 33*b873c122SLinus Walleij maxItems: 1 34*b873c122SLinus Walleij 35*b873c122SLinus Walleij interrupts: 36*b873c122SLinus Walleij maxItems: 1 37*b873c122SLinus Walleij 38*b873c122SLinus Walleij clocks: 39*b873c122SLinus Walleij minItems: 1 40*b873c122SLinus Walleij 41*b873c122SLinus Walleij clock-names: 42*b873c122SLinus Walleij const: PCLK 43*b873c122SLinus Walleij 44*b873c122SLinus Walleij sata: 45*b873c122SLinus Walleij description: 46*b873c122SLinus Walleij phandle to the Gemini PATA to SATA bridge, if available 47*b873c122SLinus Walleij $ref: /schemas/types.yaml#/definitions/phandle 48*b873c122SLinus Walleij 49*b873c122SLinus Walleijrequired: 50*b873c122SLinus Walleij - compatible 51*b873c122SLinus Walleij - reg 52*b873c122SLinus Walleij - interrupts 53*b873c122SLinus Walleij 54*b873c122SLinus WalleijallOf: 55*b873c122SLinus Walleij - $ref: pata-common.yaml# 56*b873c122SLinus Walleij 57*b873c122SLinus Walleij - if: 58*b873c122SLinus Walleij properties: 59*b873c122SLinus Walleij compatible: 60*b873c122SLinus Walleij contains: 61*b873c122SLinus Walleij const: cortina,gemini-pata 62*b873c122SLinus Walleij 63*b873c122SLinus Walleij then: 64*b873c122SLinus Walleij required: 65*b873c122SLinus Walleij - sata 66*b873c122SLinus Walleij 67*b873c122SLinus Walleijexamples: 68*b873c122SLinus Walleij - | 69*b873c122SLinus Walleij #include <dt-bindings/interrupt-controller/irq.h> 70*b873c122SLinus Walleij #include <dt-bindings/clock/cortina,gemini-clock.h> 71*b873c122SLinus Walleij 72*b873c122SLinus Walleij ide@63000000 { 73*b873c122SLinus Walleij compatible = "cortina,gemini-pata", "faraday,ftide010"; 74*b873c122SLinus Walleij reg = <0x63000000 0x100>; 75*b873c122SLinus Walleij interrupts = <4 IRQ_TYPE_EDGE_RISING>; 76*b873c122SLinus Walleij clocks = <&gcc GEMINI_CLK_GATE_IDE>; 77*b873c122SLinus Walleij clock-names = "PCLK"; 78*b873c122SLinus Walleij sata = <&sata>; 79*b873c122SLinus Walleij #address-cells = <1>; 80*b873c122SLinus Walleij #size-cells = <0>; 81*b873c122SLinus Walleij ide-port@0 { 82*b873c122SLinus Walleij reg = <0>; 83*b873c122SLinus Walleij }; 84*b873c122SLinus Walleij ide-port@1 { 85*b873c122SLinus Walleij reg = <1>; 86*b873c122SLinus Walleij }; 87*b873c122SLinus Walleij }; 88*b873c122SLinus Walleij 89*b873c122SLinus Walleij... 90