1*1ccaead5SLoc Ho* APM X-Gene 6.0 Gb/s SATA host controller nodes 2*1ccaead5SLoc Ho 3*1ccaead5SLoc HoSATA host controller nodes are defined to describe on-chip Serial ATA 4*1ccaead5SLoc Hocontrollers. Each SATA controller (pair of ports) have its own node. 5*1ccaead5SLoc Ho 6*1ccaead5SLoc HoRequired properties: 7*1ccaead5SLoc Ho- compatible : Shall contain: 8*1ccaead5SLoc Ho * "apm,xgene-ahci" 9*1ccaead5SLoc Ho- reg : First memory resource shall be the AHCI memory 10*1ccaead5SLoc Ho resource. 11*1ccaead5SLoc Ho Second memory resource shall be the host controller 12*1ccaead5SLoc Ho core memory resource. 13*1ccaead5SLoc Ho Third memory resource shall be the host controller 14*1ccaead5SLoc Ho diagnostic memory resource. 15*1ccaead5SLoc Ho 4th memory resource shall be the host controller 16*1ccaead5SLoc Ho AXI memory resource. 17*1ccaead5SLoc Ho 5th optional memory resource shall be the host 18*1ccaead5SLoc Ho controller MUX memory resource if required. 19*1ccaead5SLoc Ho- interrupts : Interrupt-specifier for SATA host controller IRQ. 20*1ccaead5SLoc Ho- clocks : Reference to the clock entry. 21*1ccaead5SLoc Ho- phys : A list of phandles + phy-specifiers, one for each 22*1ccaead5SLoc Ho entry in phy-names. 23*1ccaead5SLoc Ho- phy-names : Should contain: 24*1ccaead5SLoc Ho * "sata-phy" for the SATA 6.0Gbps PHY 25*1ccaead5SLoc Ho 26*1ccaead5SLoc HoOptional properties: 27*1ccaead5SLoc Ho- status : Shall be "ok" if enabled or "disabled" if disabled. 28*1ccaead5SLoc Ho Default is "ok". 29*1ccaead5SLoc Ho 30*1ccaead5SLoc HoExample: 31*1ccaead5SLoc Ho sataclk: sataclk { 32*1ccaead5SLoc Ho compatible = "fixed-clock"; 33*1ccaead5SLoc Ho #clock-cells = <1>; 34*1ccaead5SLoc Ho clock-frequency = <100000000>; 35*1ccaead5SLoc Ho clock-output-names = "sataclk"; 36*1ccaead5SLoc Ho }; 37*1ccaead5SLoc Ho 38*1ccaead5SLoc Ho phy2: phy@1f22a000 { 39*1ccaead5SLoc Ho compatible = "apm,xgene-phy"; 40*1ccaead5SLoc Ho reg = <0x0 0x1f22a000 0x0 0x100>; 41*1ccaead5SLoc Ho #phy-cells = <1>; 42*1ccaead5SLoc Ho }; 43*1ccaead5SLoc Ho 44*1ccaead5SLoc Ho phy3: phy@1f23a000 { 45*1ccaead5SLoc Ho compatible = "apm,xgene-phy"; 46*1ccaead5SLoc Ho reg = <0x0 0x1f23a000 0x0 0x100>; 47*1ccaead5SLoc Ho #phy-cells = <1>; 48*1ccaead5SLoc Ho }; 49*1ccaead5SLoc Ho 50*1ccaead5SLoc Ho sata2: sata@1a400000 { 51*1ccaead5SLoc Ho compatible = "apm,xgene-ahci"; 52*1ccaead5SLoc Ho reg = <0x0 0x1a400000 0x0 0x1000>, 53*1ccaead5SLoc Ho <0x0 0x1f220000 0x0 0x1000>, 54*1ccaead5SLoc Ho <0x0 0x1f22d000 0x0 0x1000>, 55*1ccaead5SLoc Ho <0x0 0x1f22e000 0x0 0x1000>, 56*1ccaead5SLoc Ho <0x0 0x1f227000 0x0 0x1000>; 57*1ccaead5SLoc Ho interrupts = <0x0 0x87 0x4>; 58*1ccaead5SLoc Ho status = "ok"; 59*1ccaead5SLoc Ho clocks = <&sataclk 0>; 60*1ccaead5SLoc Ho phys = <&phy2 0>; 61*1ccaead5SLoc Ho phy-names = "sata-phy"; 62*1ccaead5SLoc Ho }; 63*1ccaead5SLoc Ho 64*1ccaead5SLoc Ho sata3: sata@1a800000 { 65*1ccaead5SLoc Ho compatible = "apm,xgene-ahci-pcie"; 66*1ccaead5SLoc Ho reg = <0x0 0x1a800000 0x0 0x1000>, 67*1ccaead5SLoc Ho <0x0 0x1f230000 0x0 0x1000>, 68*1ccaead5SLoc Ho <0x0 0x1f23d000 0x0 0x1000>, 69*1ccaead5SLoc Ho <0x0 0x1f23e000 0x0 0x1000>, 70*1ccaead5SLoc Ho <0x0 0x1f237000 0x0 0x1000>; 71*1ccaead5SLoc Ho interrupts = <0x0 0x88 0x4>; 72*1ccaead5SLoc Ho status = "ok"; 73*1ccaead5SLoc Ho clocks = <&sataclk 0>; 74*1ccaead5SLoc Ho phys = <&phy3 0>; 75*1ccaead5SLoc Ho phy-names = "sata-phy"; 76*1ccaead5SLoc Ho }; 77