xref: /linux/Documentation/devicetree/bindings/ata/ahci-platform.yaml (revision 1fd1dc41724319406b0aff221a352a400b0ddfc5) 
1# SPDX-License-Identifier: GPL-2.0
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/ata/ahci-platform.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: AHCI SATA Controller
8
9description: |
10  SATA nodes are defined to describe on-chip Serial ATA controllers.
11  Each SATA controller should have its own node.
12
13  It is possible, but not required, to represent each port as a sub-node.
14  It allows to enable each port independently when dealing with multiple
15  PHYs.
16
17maintainers:
18  - Hans de Goede <hdegoede@redhat.com>
19  - Jens Axboe <axboe@kernel.dk>
20
21properties:
22  compatible:
23    oneOf:
24      - items:
25          - enum:
26              - brcm,iproc-ahci
27              - marvell,armada-8k-ahci
28              - marvell,berlin2-ahci
29              - marvell,berlin2q-ahci
30              - qcom,apq8064-ahci
31              - qcom,ipq806x-ahci
32              - socionext,uniphier-pro4-ahci
33              - socionext,uniphier-pxs2-ahci
34              - socionext,uniphier-pxs3-ahci
35          - const: generic-ahci
36      - enum:
37          - cavium,octeon-7130-ahci
38          - hisilicon,hisi-ahci
39          - ibm,476gtr-ahci
40          - marvell,armada-3700-ahci
41
42  reg:
43    minItems: 1
44    maxItems: 2
45
46  reg-names:
47    maxItems: 1
48
49  clocks:
50    minItems: 1
51    maxItems: 5
52
53  clock-names:
54    minItems: 1
55    maxItems: 5
56
57  interrupts:
58    maxItems: 1
59
60  power-domains:
61    maxItems: 1
62
63  resets:
64    minItems: 1
65    maxItems: 3
66
67  iommus:
68    maxItems: 1
69
70patternProperties:
71  "^sata-port@[0-9a-f]+$":
72    $ref: /schemas/ata/ahci-common.yaml#/$defs/ahci-port
73
74    anyOf:
75      - required: [ phys ]
76      - required: [ target-supply ]
77
78    unevaluatedProperties: false
79
80required:
81  - compatible
82  - reg
83  - interrupts
84
85allOf:
86  - $ref: ahci-common.yaml#
87
88  - if:
89      properties:
90        compatible:
91          contains:
92            enum:
93              - qcom,apq8064-ahci
94              - qcom,ipq806x-ahci
95    then:
96      properties:
97        clocks:
98          minItems: 5
99        clock-names:
100          items:
101            - const: slave_iface
102            - const: iface
103            - const: core
104            - const: rxoob
105            - const: pmalive
106      required:
107        - phys
108        - phy-names
109        - clocks
110        - clock-names
111
112  - if:
113      properties:
114        compatible:
115          contains:
116            const: socionext,uniphier-pro4-ahci
117    then:
118      properties:
119        resets:
120          items:
121            - description: reset line for the parent
122            - description: reset line for the glue logic
123            - description: reset line for the controller
124      required:
125        - resets
126    else:
127      if:
128        properties:
129          compatible:
130            contains:
131              enum:
132                - socionext,uniphier-pxs2-ahci
133                - socionext,uniphier-pxs3-ahci
134      then:
135        properties:
136          resets:
137            items:
138              - description: reset for the glue logic
139              - description: reset for the controller
140        required:
141          - resets
142      else:
143        properties:
144          resets:
145            maxItems: 1
146
147unevaluatedProperties: false
148
149examples:
150  - |
151    sata@ffe08000 {
152        compatible = "snps,spear-ahci";
153        reg = <0xffe08000 0x1000>;
154        interrupts = <115>;
155    };
156  - |
157    #include <dt-bindings/interrupt-controller/arm-gic.h>
158    #include <dt-bindings/clock/berlin2q.h>
159    #include <dt-bindings/ata/ahci.h>
160
161    sata@f7e90000 {
162        compatible = "marvell,berlin2q-ahci", "generic-ahci";
163        reg = <0xf7e90000 0x1000>;
164        interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
165        clocks = <&chip CLKID_SATA>;
166        #address-cells = <1>;
167        #size-cells = <0>;
168
169        hba-cap = <HBA_SMPS>;
170
171        sata0: sata-port@0 {
172            reg = <0>;
173
174            phys = <&sata_phy 0>;
175            target-supply = <&reg_sata0>;
176
177            hba-port-cap = <(HBA_PORT_FBSCP | HBA_PORT_ESP)>;
178        };
179
180        sata1: sata-port@1 {
181            reg = <1>;
182
183            phys = <&sata_phy 1>;
184            target-supply = <&reg_sata1>;
185
186            hba-port-cap = <(HBA_PORT_HPCP | HBA_PORT_MPSP | HBA_PORT_FBSCP)>;
187        };
188    };
189