1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/arm/tegra/nvidia,tegra186-pmc.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: NVIDIA Tegra Power Management Controller (PMC) 8 9maintainers: 10 - Thierry Reding <thierry.reding@gmail.com> 11 - Jon Hunter <jonathanh@nvidia.com> 12 13properties: 14 compatible: 15 enum: 16 - nvidia,tegra186-pmc 17 - nvidia,tegra194-pmc 18 - nvidia,tegra234-pmc 19 20 reg: 21 minItems: 4 22 maxItems: 5 23 24 reg-names: 25 minItems: 4 26 items: 27 - const: pmc 28 - const: wake 29 - const: aotag 30 - enum: [ scratch, misc ] 31 - const: misc 32 33 interrupt-controller: true 34 35 "#interrupt-cells": 36 description: Specifies the number of cells needed to encode an 37 interrupt source. The value must be 2. 38 const: 2 39 40 nvidia,invert-interrupt: 41 description: If present, inverts the PMU interrupt signal. 42 $ref: /schemas/types.yaml#/definitions/flag 43 44allOf: 45 - if: 46 properties: 47 compatible: 48 contains: 49 const: nvidia,tegra186-pmc 50 then: 51 properties: 52 reg: 53 maxItems: 4 54 reg-names: 55 maxItems: 4 56 contains: 57 const: scratch 58 59 - if: 60 properties: 61 compatible: 62 contains: 63 const: nvidia,tegra194-pmc 64 then: 65 properties: 66 reg: 67 minItems: 5 68 reg-names: 69 minItems: 5 70 71 - if: 72 properties: 73 compatible: 74 contains: 75 const: nvidia,tegra234-pmc 76 then: 77 properties: 78 reg-names: 79 contains: 80 const: misc 81 82patternProperties: 83 "^[a-z0-9]+-[a-z0-9]+$": 84 if: 85 type: object 86 then: 87 description: | 88 These are pad configuration nodes. On Tegra SoCs a pad is a set of 89 pins which are configured as a group. The pin grouping is a fixed 90 attribute of the hardware. The PMC can be used to set pad power 91 state and signaling voltage. A pad can be either in active or 92 power down mode. The support for power state and signaling voltage 93 configuration varies depending on the pad in question. 3.3 V and 94 1.8 V signaling voltages are supported on pins where software 95 controllable signaling voltage switching is available. 96 97 Pad configurations are described with pin configuration nodes 98 which are placed under the pmc node and they are referred to by 99 the pinctrl client properties. For more information see 100 101 Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt 102 103 The following pads are present on Tegra186: 104 105 csia, csib, dsi, mipi-bias, pex-clk-bias, pex-clk3, pex-clk2, 106 pex-clk1, usb0, usb1, usb2, usb-bias, uart, audio, hsic, dbg, 107 hdmi-dp0, hdmi-dp1, pex-cntrl, sdmmc2-hv, sdmmc4, cam, dsib, 108 dsic, dsid, csic, csid, csie, dsif, spi, ufs, dmic-hv, edp, 109 sdmmc1-hv, sdmmc3-hv, conn, audio-hv, ao-hv 110 111 The following pads are present on Tegra194: 112 113 csia, csib, mipi-bias, pex-clk-bias, pex-clk3, pex-clk2, 114 pex-clk1, eqos, pex-clk-2-bias, pex-clk-2, dap3, dap5, uart, 115 pwr-ctl, soc-gpio53, audio, gp-pwm2, gp-pwm3, soc-gpio12, 116 soc-gpio13, soc-gpio10, uart4, uart5, dbg, hdmi-dp3, hdmi-dp2, 117 hdmi-dp0, hdmi-dp1, pex-cntrl, pex-ctl2, pex-l0-rst, 118 pex-l1-rst, sdmmc4, pex-l5-rst, cam, csic, csid, csie, csif, 119 spi, ufs, csig, csih, edp, sdmmc1-hv, sdmmc3-hv, conn, 120 audio-hv, ao-hv 121 122 properties: 123 pins: 124 $ref: /schemas/types.yaml#/definitions/string 125 description: Must contain the name of the pad(s) to be 126 configured. 127 128 low-power-enable: 129 description: Configure the pad into power down mode. 130 $ref: /schemas/types.yaml#/definitions/flag 131 132 low-power-disable: 133 description: Configure the pad into active mode. 134 $ref: /schemas/types.yaml#/definitions/flag 135 136 power-source: 137 $ref: /schemas/types.yaml#/definitions/uint32 138 description: | 139 Must contain either TEGRA_IO_PAD_VOLTAGE_1V8 or 140 TEGRA_IO_PAD_VOLTAGE_3V3 to select between signalling 141 voltages. 142 143 The values are defined in 144 145 include/dt-bindings/pinctrl/pinctrl-tegra-io-pad.h 146 147 The power state can be configured on all of the above pads 148 except for ao-hv. Following pads have software configurable 149 signaling voltages: sdmmc2-hv, dmic-hv, sdmmc1-hv, sdmmc3-hv, 150 audio-hv, ao-hv. 151 152 phandle: true 153 154 required: 155 - pins 156 157 additionalProperties: false 158 159required: 160 - compatible 161 - reg 162 - reg-names 163 164additionalProperties: false 165 166dependencies: 167 interrupt-controller: ['#interrupt-cells'] 168 "#interrupt-cells": 169 required: 170 - interrupt-controller 171 172examples: 173 - | 174 #include <dt-bindings/clock/tegra186-clock.h> 175 #include <dt-bindings/interrupt-controller/arm-gic.h> 176 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h> 177 #include <dt-bindings/memory/tegra186-mc.h> 178 #include <dt-bindings/reset/tegra186-reset.h> 179 180 pmc@c3600000 { 181 compatible = "nvidia,tegra186-pmc"; 182 reg = <0x0c360000 0x10000>, 183 <0x0c370000 0x10000>, 184 <0x0c380000 0x10000>, 185 <0x0c390000 0x10000>; 186 reg-names = "pmc", "wake", "aotag", "scratch"; 187 nvidia,invert-interrupt; 188 189 sdmmc1_3v3: sdmmc1-3v3 { 190 pins = "sdmmc1-hv"; 191 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 192 }; 193 194 sdmmc1_1v8: sdmmc1-1v8 { 195 pins = "sdmmc1-hv"; 196 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 197 }; 198 }; 199 200 sdmmc1: mmc@3400000 { 201 compatible = "nvidia,tegra186-sdhci"; 202 reg = <0x03400000 0x10000>; 203 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 204 clocks = <&bpmp TEGRA186_CLK_SDMMC1>, 205 <&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>; 206 clock-names = "sdhci", "tmclk"; 207 resets = <&bpmp TEGRA186_RESET_SDMMC1>; 208 reset-names = "sdhci"; 209 interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCRA &emc>, 210 <&mc TEGRA186_MEMORY_CLIENT_SDMMCWA &emc>; 211 interconnect-names = "dma-mem", "write"; 212 iommus = <&smmu TEGRA186_SID_SDMMC1>; 213 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 214 pinctrl-0 = <&sdmmc1_3v3>; 215 pinctrl-1 = <&sdmmc1_1v8>; 216 }; 217