1Synaptics SoC Device Tree Bindings 2 3According to https://www.synaptics.com/company/news/conexant-marvell 4Synaptics has acquired the Multimedia Solutions Business of Marvell, so 5berlin SoCs are now Synaptics' SoCs now. 6 7--------------------------------------------------------------- 8 9Boards with a SoC of the Marvell Berlin family, e.g. Armada 1500 10shall have the following properties: 11 12* Required root node properties: 13compatible: must contain "marvell,berlin" 14 15In addition, the above compatible shall be extended with the specific 16SoC and board used. Currently known SoC compatibles are: 17 "marvell,berlin2" for Marvell Armada 1500 (BG2, 88DE3100), 18 "marvell,berlin2cd" for Marvell Armada 1500-mini (BG2CD, 88DE3005) 19 "marvell,berlin2ct" for Marvell Armada ? (BG2CT, 88DE????) 20 "marvell,berlin2q" for Marvell Armada 1500-pro (BG2Q, 88DE3114) 21 "marvell,berlin3" for Marvell Armada ? (BG3, 88DE????) 22 23* Example: 24 25/ { 26 model = "Sony NSZ-GS7"; 27 compatible = "sony,nsz-gs7", "marvell,berlin2", "marvell,berlin"; 28 29 ... 30} 31 32* Marvell Berlin CPU control bindings 33 34CPU control register allows various operations on CPUs, like resetting them 35independently. 36 37Required properties: 38- compatible: should be "marvell,berlin-cpu-ctrl" 39- reg: address and length of the register set 40 41Example: 42 43cpu-ctrl@f7dd0000 { 44 compatible = "marvell,berlin-cpu-ctrl"; 45 reg = <0xf7dd0000 0x10000>; 46}; 47 48* Marvell Berlin2 chip control binding 49 50Marvell Berlin SoCs have a chip control register set providing several 51individual registers dealing with pinmux, padmux, clock, reset, and secondary 52CPU boot address. Unfortunately, the individual registers are spread among the 53chip control registers, so there should be a single DT node only providing the 54different functions which are described below. 55 56Required properties: 57- compatible: 58 * the first and second values must be: 59 "simple-mfd", "syscon" 60- reg: address and length of following register sets for 61 BG2/BG2CD: chip control register set 62 BG2Q: chip control register set and cpu pll registers 63 64* Marvell Berlin2 system control binding 65 66Marvell Berlin SoCs have a system control register set providing several 67individual registers dealing with pinmux, padmux, and reset. 68 69Required properties: 70- compatible: 71 * the first and second values must be: 72 "simple-mfd", "syscon" 73- reg: address and length of the system control register set 74 75Example: 76 77chip: chip-control@ea0000 { 78 compatible = "simple-mfd", "syscon"; 79 reg = <0xea0000 0x400>; 80 81 /* sub-device nodes */ 82}; 83 84sysctrl: system-controller@d000 { 85 compatible = "simple-mfd", "syscon"; 86 reg = <0xd000 0x100>; 87 88 /* sub-device nodes */ 89}; 90