1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/arm/qcom,coresight-ctcu.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: CoreSight TMC Control Unit 8 9maintainers: 10 - Yuanfang Zhang <quic_yuanfang@quicinc.com> 11 - Mao Jinlong <quic_jinlmao@quicinc.com> 12 - Jie Gan <quic_jiegan@quicinc.com> 13 14description: | 15 The Trace Memory Controller(TMC) is used for Embedded Trace Buffer(ETB), 16 Embedded Trace FIFO(ETF) and Embedded Trace Router(ETR) configurations. 17 The configuration mode (ETB, ETF, ETR) is discovered at boot time when 18 the device is probed. 19 20 The Coresight TMC Control unit controls various Coresight behaviors. 21 It works as a helper device when connected to TMC ETR device. 22 It is responsible for controlling the data filter function based on 23 the source device's Trace ID for TMC ETR device. The trace data with 24 that Trace id can get into ETR's buffer while other trace data gets 25 ignored. 26 27properties: 28 compatible: 29 enum: 30 - qcom,sa8775p-ctcu 31 32 reg: 33 maxItems: 1 34 35 clocks: 36 maxItems: 1 37 38 clock-names: 39 items: 40 - const: apb 41 42 label: 43 description: 44 Description of a coresight device. 45 46 in-ports: 47 $ref: /schemas/graph.yaml#/properties/ports 48 49 patternProperties: 50 '^port(@[0-1])?$': 51 description: Input connections from CoreSight Trace bus 52 $ref: /schemas/graph.yaml#/properties/port 53 54required: 55 - compatible 56 - reg 57 - in-ports 58 59additionalProperties: false 60 61examples: 62 - | 63 ctcu@1001000 { 64 compatible = "qcom,sa8775p-ctcu"; 65 reg = <0x1001000 0x1000>; 66 67 clocks = <&aoss_qmp>; 68 clock-names = "apb"; 69 70 in-ports { 71 #address-cells = <1>; 72 #size-cells = <0>; 73 74 port@0 { 75 reg = <0>; 76 ctcu_in_port0: endpoint { 77 remote-endpoint = <&etr0_out_port>; 78 }; 79 }; 80 81 port@1 { 82 reg = <1>; 83 ctcu_in_port1: endpoint { 84 remote-endpoint = <&etr1_out_port>; 85 }; 86 }; 87 }; 88 }; 89