1476b679aSBenoit Cousson* TI - MPU (Main Processor Unit) subsystem 2476b679aSBenoit Cousson 3476b679aSBenoit CoussonThe MPU subsystem contain one or several ARM cores 4476b679aSBenoit Coussondepending of the version. 5476b679aSBenoit CoussonThe MPU contain CPUs, GIC, L2 cache and a local PRCM. 6476b679aSBenoit Cousson 7476b679aSBenoit CoussonRequired properties: 8476b679aSBenoit Cousson- compatible : Should be "ti,omap3-mpu" for OMAP3 9476b679aSBenoit Cousson Should be "ti,omap4-mpu" for OMAP4 10f1e8e381SSricharan R Should be "ti,omap5-mpu" for OMAP5 11476b679aSBenoit Cousson- ti,hwmods: "mpu" 12476b679aSBenoit Cousson 13*1306c08aSRajendra NayakOptional properties: 14*1306c08aSRajendra Nayak- sram: Phandle to the ocmcram node 15*1306c08aSRajendra Nayak 16476b679aSBenoit CoussonExamples: 17476b679aSBenoit Cousson 18f1e8e381SSricharan R- For an OMAP5 SMP system: 19f1e8e381SSricharan R 20f1e8e381SSricharan Rmpu { 21f1e8e381SSricharan R compatible = "ti,omap5-mpu"; 22f1e8e381SSricharan R ti,hwmods = "mpu" 23f1e8e381SSricharan R}; 24f1e8e381SSricharan R 25476b679aSBenoit Cousson- For an OMAP4 SMP system: 26476b679aSBenoit Cousson 27476b679aSBenoit Coussonmpu { 28476b679aSBenoit Cousson compatible = "ti,omap4-mpu"; 29476b679aSBenoit Cousson ti,hwmods = "mpu"; 30476b679aSBenoit Cousson}; 31476b679aSBenoit Cousson 32476b679aSBenoit Cousson 33476b679aSBenoit Cousson- For an OMAP3 monocore system: 34476b679aSBenoit Cousson 35476b679aSBenoit Coussonmpu { 36476b679aSBenoit Cousson compatible = "ti,omap3-mpu"; 37476b679aSBenoit Cousson ti,hwmods = "mpu"; 38476b679aSBenoit Cousson}; 39