xref: /linux/Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.yaml (revision 1fd1dc41724319406b0aff221a352a400b0ddfc5) 
1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/arm/mediatek/mediatek,audsys.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: MediaTek AUDSYS controller
8
9maintainers:
10  - Eugen Hristev <eugen.hristev@collabora.com>
11
12description:
13  The MediaTek AUDSYS controller provides various clocks to the system.
14
15properties:
16  compatible:
17    oneOf:
18      - items:
19          - enum:
20              - mediatek,mt2701-audsys
21              - mediatek,mt6765-audsys
22              - mediatek,mt6779-audsys
23              - mediatek,mt7622-audsys
24              - mediatek,mt8167-audsys
25              - mediatek,mt8173-audsys
26              - mediatek,mt8183-audiosys
27              - mediatek,mt8183-audsys
28              - mediatek,mt8186-audsys
29              - mediatek,mt8192-audsys
30              - mediatek,mt8516-audsys
31          - const: syscon
32      - items:
33          # Special case for mt7623 for backward compatibility
34          - const: mediatek,mt7623-audsys
35          - const: mediatek,mt2701-audsys
36          - const: syscon
37
38  reg:
39    maxItems: 1
40
41  '#clock-cells':
42    const: 1
43
44  audio-controller:
45    type: object
46
47required:
48  - compatible
49  - '#clock-cells'
50
51allOf:
52 - if:
53     properties:
54       compatible:
55         contains:
56           enum:
57             - mediatek,mt2701-audsys
58             - mediatek,mt7622-audsys
59   then:
60     properties:
61       audio-controller:
62         $ref: /schemas/sound/mediatek,mt2701-audio.yaml#
63
64 - if:
65     properties:
66       compatible:
67         contains:
68           const: mediatek,mt8183-audiosys
69   then:
70     properties:
71       audio-controller:
72         $ref: /schemas/sound/mediatek,mt8183-audio.yaml#
73
74 - if:
75     properties:
76       compatible:
77         contains:
78           const: mediatek,mt8192-audsys
79   then:
80     properties:
81       audio-controller:
82         $ref: /schemas/sound/mt8192-afe-pcm.yaml#
83
84
85additionalProperties: false
86
87examples:
88  - |
89    #include <dt-bindings/interrupt-controller/arm-gic.h>
90    #include <dt-bindings/interrupt-controller/irq.h>
91    #include <dt-bindings/power/mt2701-power.h>
92    #include <dt-bindings/clock/mt2701-clk.h>
93    soc {
94        #address-cells = <2>;
95        #size-cells = <2>;
96        audsys: clock-controller@11220000 {
97            compatible = "mediatek,mt7622-audsys", "syscon";
98            reg = <0 0x11220000 0 0x2000>;
99            #clock-cells = <1>;
100
101            afe: audio-controller {
102                compatible = "mediatek,mt2701-audio";
103                interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>,
104                             <GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>;
105                interrupt-names = "afe", "asys";
106                power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;
107
108                clocks = <&infracfg CLK_INFRA_AUDIO>,
109                         <&topckgen CLK_TOP_AUD_MUX1_SEL>,
110                         <&topckgen CLK_TOP_AUD_MUX2_SEL>,
111                         <&topckgen CLK_TOP_AUD_48K_TIMING>,
112                         <&topckgen CLK_TOP_AUD_44K_TIMING>,
113                         <&topckgen CLK_TOP_AUD_K1_SRC_SEL>,
114                         <&topckgen CLK_TOP_AUD_K2_SRC_SEL>,
115                         <&topckgen CLK_TOP_AUD_K3_SRC_SEL>,
116                         <&topckgen CLK_TOP_AUD_K4_SRC_SEL>,
117                         <&topckgen CLK_TOP_AUD_K1_SRC_DIV>,
118                         <&topckgen CLK_TOP_AUD_K2_SRC_DIV>,
119                         <&topckgen CLK_TOP_AUD_K3_SRC_DIV>,
120                         <&topckgen CLK_TOP_AUD_K4_SRC_DIV>,
121                         <&topckgen CLK_TOP_AUD_I2S1_MCLK>,
122                         <&topckgen CLK_TOP_AUD_I2S2_MCLK>,
123                         <&topckgen CLK_TOP_AUD_I2S3_MCLK>,
124                         <&topckgen CLK_TOP_AUD_I2S4_MCLK>,
125                         <&audsys CLK_AUD_I2SO1>,
126                         <&audsys CLK_AUD_I2SO2>,
127                         <&audsys CLK_AUD_I2SO3>,
128                         <&audsys CLK_AUD_I2SO4>,
129                         <&audsys CLK_AUD_I2SIN1>,
130                         <&audsys CLK_AUD_I2SIN2>,
131                         <&audsys CLK_AUD_I2SIN3>,
132                         <&audsys CLK_AUD_I2SIN4>,
133                         <&audsys CLK_AUD_ASRCO1>,
134                         <&audsys CLK_AUD_ASRCO2>,
135                         <&audsys CLK_AUD_ASRCO3>,
136                         <&audsys CLK_AUD_ASRCO4>,
137                         <&audsys CLK_AUD_AFE>,
138                         <&audsys CLK_AUD_AFE_CONN>,
139                         <&audsys CLK_AUD_A1SYS>,
140                         <&audsys CLK_AUD_A2SYS>,
141                         <&audsys CLK_AUD_AFE_MRGIF>;
142
143                clock-names = "infra_sys_audio_clk",
144                              "top_audio_mux1_sel",
145                              "top_audio_mux2_sel",
146                              "top_audio_a1sys_hp",
147                              "top_audio_a2sys_hp",
148                              "i2s0_src_sel",
149                              "i2s1_src_sel",
150                              "i2s2_src_sel",
151                              "i2s3_src_sel",
152                              "i2s0_src_div",
153                              "i2s1_src_div",
154                              "i2s2_src_div",
155                              "i2s3_src_div",
156                              "i2s0_mclk_en",
157                              "i2s1_mclk_en",
158                              "i2s2_mclk_en",
159                              "i2s3_mclk_en",
160                              "i2so0_hop_ck",
161                              "i2so1_hop_ck",
162                              "i2so2_hop_ck",
163                              "i2so3_hop_ck",
164                              "i2si0_hop_ck",
165                              "i2si1_hop_ck",
166                              "i2si2_hop_ck",
167                              "i2si3_hop_ck",
168                              "asrc0_out_ck",
169                              "asrc1_out_ck",
170                              "asrc2_out_ck",
171                              "asrc3_out_ck",
172                              "audio_afe_pd",
173                              "audio_afe_conn_pd",
174                              "audio_a1sys_pd",
175                              "audio_a2sys_pd",
176                              "audio_mrgif_pd";
177
178                assigned-clocks = <&topckgen CLK_TOP_AUD_MUX1_SEL>,
179                                  <&topckgen CLK_TOP_AUD_MUX2_SEL>,
180                                  <&topckgen CLK_TOP_AUD_MUX1_DIV>,
181                                  <&topckgen CLK_TOP_AUD_MUX2_DIV>;
182                assigned-clock-parents = <&topckgen CLK_TOP_AUD1PLL_98M>,
183                                         <&topckgen CLK_TOP_AUD2PLL_90M>;
184                assigned-clock-rates = <0>, <0>, <49152000>, <45158400>;
185            };
186        };
187    };
188