1*47b65a4aSSean WangMediaTek g3dsys controller 2*47b65a4aSSean Wang============================ 3*47b65a4aSSean Wang 4*47b65a4aSSean WangThe MediaTek g3dsys controller provides various clocks and reset controller to 5*47b65a4aSSean Wangthe GPU. 6*47b65a4aSSean Wang 7*47b65a4aSSean WangRequired Properties: 8*47b65a4aSSean Wang 9*47b65a4aSSean Wang- compatible: Should be: 10*47b65a4aSSean Wang - "mediatek,mt2701-g3dsys", "syscon": 11*47b65a4aSSean Wang for MT2701 SoC 12*47b65a4aSSean Wang - "mediatek,mt7623-g3dsys", "mediatek,mt2701-g3dsys", "syscon": 13*47b65a4aSSean Wang for MT7623 SoC 14*47b65a4aSSean Wang- #clock-cells: Must be 1 15*47b65a4aSSean Wang- #reset-cells: Must be 1 16*47b65a4aSSean Wang 17*47b65a4aSSean WangThe g3dsys controller uses the common clk binding from 18*47b65a4aSSean WangDocumentation/devicetree/bindings/clock/clock-bindings.txt 19*47b65a4aSSean WangThe available clocks are defined in dt-bindings/clock/mt*-clk.h. 20*47b65a4aSSean Wang 21*47b65a4aSSean WangExample: 22*47b65a4aSSean Wang 23*47b65a4aSSean Wangg3dsys: clock-controller@13000000 { 24*47b65a4aSSean Wang compatible = "mediatek,mt7623-g3dsys", 25*47b65a4aSSean Wang "mediatek,mt2701-g3dsys", 26*47b65a4aSSean Wang "syscon"; 27*47b65a4aSSean Wang reg = <0 0x13000000 0 0x200>; 28*47b65a4aSSean Wang #clock-cells = <1>; 29*47b65a4aSSean Wang #reset-cells = <1>; 30*47b65a4aSSean Wang}; 31