1# SPDX-License-Identifier: GPL-2.0 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/arm/cpus.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: ARM CPUs 8 9maintainers: 10 - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> 11 12description: |+ 13 The device tree allows to describe the layout of CPUs in a system through the 14 "cpus" node, which in turn contains a number of subnodes (ie "cpu") defining 15 properties for every cpu. 16 17 Bindings for CPU nodes follow the Devicetree Specification, available from: 18 19 https://www.devicetree.org/specifications/ 20 21 with updates for 32-bit and 64-bit ARM systems provided in this document. 22 23 ================================ 24 Convention used in this document 25 ================================ 26 27 This document follows the conventions described in the Devicetree 28 Specification, with the addition: 29 30 - square brackets define bitfields, eg reg[7:0] value of the bitfield in 31 the reg property contained in bits 7 down to 0 32 33 ===================================== 34 cpus and cpu node bindings definition 35 ===================================== 36 37 The ARM architecture, in accordance with the Devicetree Specification, 38 requires the cpus and cpu nodes to be present and contain the properties 39 described below. 40 41properties: 42 reg: 43 maxItems: 1 44 description: > 45 Usage and definition depend on ARM architecture version and configuration: 46 47 On uniprocessor ARM architectures previous to v7 this property is required 48 and must be set to 0. 49 50 On ARM 11 MPcore based systems this property is required and matches the 51 CPUID[11:0] register bits. 52 53 Bits [11:0] in the reg cell must be set to bits [11:0] in CPU ID register. 54 55 All other bits in the reg cell must be set to 0. 56 57 On 32-bit ARM v7 or later systems this property is required and matches 58 the CPU MPIDR[23:0] register bits. 59 60 Bits [23:0] in the reg cell must be set to bits [23:0] in MPIDR. 61 62 All other bits in the reg cell must be set to 0. 63 64 On ARM v8 64-bit systems this property is required and matches the 65 MPIDR_EL1 register affinity bits. 66 67 * If cpus node's #address-cells property is set to 2 68 69 The first reg cell bits [7:0] must be set to bits [39:32] of 70 MPIDR_EL1. 71 72 The second reg cell bits [23:0] must be set to bits [23:0] of 73 MPIDR_EL1. 74 75 * If cpus node's #address-cells property is set to 1 76 77 The reg cell bits [23:0] must be set to bits [23:0] of MPIDR_EL1. 78 79 All other bits in the reg cells must be set to 0. 80 81 compatible: 82 oneOf: 83 - enum: 84 - apm,potenza 85 - apm,strega 86 - apple,avalanche 87 - apple,blizzard 88 - apple,cyclone 89 - apple,everest 90 - apple,firestorm 91 - apple,hurricane-zephyr 92 - apple,icestorm 93 - apple,mistral 94 - apple,monsoon 95 - apple,sawtooth 96 - apple,twister 97 - apple,typhoon 98 - arm,arm710t 99 - arm,arm720t 100 - arm,arm740t 101 - arm,arm7ej-s 102 - arm,arm7tdmi 103 - arm,arm7tdmi-s 104 - arm,arm9es 105 - arm,arm9ej-s 106 - arm,arm920t 107 - arm,arm922t 108 - arm,arm925 109 - arm,arm926e-s 110 - arm,arm926ej-s 111 - arm,arm940t 112 - arm,arm946e-s 113 - arm,arm966e-s 114 - arm,arm968e-s 115 - arm,arm9tdmi 116 - arm,arm1020e 117 - arm,arm1020t 118 - arm,arm1022e 119 - arm,arm1026ej-s 120 - arm,arm1136j-s 121 - arm,arm1136jf-s 122 - arm,arm1156t2-s 123 - arm,arm1156t2f-s 124 - arm,arm1176jzf 125 - arm,arm1176jz-s 126 - arm,arm1176jzf-s 127 - arm,arm11mpcore 128 - arm,armv8 # Only for s/w models 129 - arm,c1-nano 130 - arm,c1-premium 131 - arm,c1-pro 132 - arm,c1-ultra 133 - arm,cortex-a5 134 - arm,cortex-a7 135 - arm,cortex-a8 136 - arm,cortex-a9 137 - arm,cortex-a12 138 - arm,cortex-a15 139 - arm,cortex-a17 140 - arm,cortex-a32 141 - arm,cortex-a34 142 - arm,cortex-a35 143 - arm,cortex-a53 144 - arm,cortex-a55 145 - arm,cortex-a57 146 - arm,cortex-a65 147 - arm,cortex-a72 148 - arm,cortex-a73 149 - arm,cortex-a75 150 - arm,cortex-a76 151 - arm,cortex-a77 152 - arm,cortex-a78 153 - arm,cortex-a78ae 154 - arm,cortex-a78c 155 - arm,cortex-a320 156 - arm,cortex-a510 157 - arm,cortex-a520 158 - arm,cortex-a520ae 159 - arm,cortex-a710 160 - arm,cortex-a715 161 - arm,cortex-a720 162 - arm,cortex-a720ae 163 - arm,cortex-a725 164 - arm,cortex-m0 165 - arm,cortex-m0+ 166 - arm,cortex-m1 167 - arm,cortex-m3 168 - arm,cortex-m4 169 - arm,cortex-r4 170 - arm,cortex-r5 171 - arm,cortex-r7 172 - arm,cortex-r52 173 - arm,cortex-x1 174 - arm,cortex-x1c 175 - arm,cortex-x2 176 - arm,cortex-x3 177 - arm,cortex-x4 178 - arm,cortex-x925 179 - arm,neoverse-e1 180 - arm,neoverse-n1 181 - arm,neoverse-n2 182 - arm,neoverse-n3 183 - arm,neoverse-v1 184 - arm,neoverse-v2 185 - arm,neoverse-v3 186 - arm,neoverse-v3ae 187 - arm,rainier 188 - brcm,brahma-b15 189 - brcm,brahma-b53 190 - brcm,vulcan 191 - cavium,thunder 192 - cavium,thunder2 193 - faraday,fa526 194 - intel,sa110 195 - intel,sa1100 196 - marvell,feroceon 197 - marvell,mohawk 198 - marvell,pj4a 199 - marvell,pj4b 200 - marvell,sheeva-v5 201 - marvell,sheeva-v7 202 - nvidia,tegra132-denver 203 - nvidia,tegra186-denver 204 - nvidia,tegra194-carmel 205 - qcom,krait 206 - qcom,kryo240 207 - qcom,kryo250 208 - qcom,kryo260 209 - qcom,kryo280 210 - qcom,kryo360 211 - qcom,kryo385 212 - qcom,kryo465 213 - qcom,kryo468 214 - qcom,kryo470 215 - qcom,kryo485 216 - qcom,kryo560 217 - qcom,kryo570 218 - qcom,kryo660 219 - qcom,kryo670 220 - qcom,kryo685 221 - qcom,kryo780 222 - qcom,oryon-1-1 223 - qcom,oryon-1-2 224 - qcom,oryon-1-3 225 - qcom,oryon-1-4 226 - qcom,oryon-1-5 227 - qcom,oryon-2-1 228 - qcom,oryon-2-2 229 - qcom,oryon-2-3 230 - qcom,scorpion 231 - samsung,mongoose-m2 232 - samsung,mongoose-m3 233 - samsung,mongoose-m5 234 - enum: 235 - qcom,kryo 236 - qcom,oryon 237 # Too generic, do not use in new code 238 deprecated: true 239 240 enable-method: 241 $ref: /schemas/types.yaml#/definitions/string 242 oneOf: 243 # On ARM v8 64-bit this property is required 244 - enum: 245 - psci 246 - spin-table 247 # On ARM 32-bit systems this property is optional 248 - enum: 249 - actions,s500-smp 250 - allwinner,sun6i-a31 251 - allwinner,sun8i-a23 252 - allwinner,sun9i-a80-smp 253 - allwinner,sun8i-a83t-smp 254 - amlogic,meson8-smp 255 - amlogic,meson8b-smp 256 - arm,realview-smp 257 - aspeed,ast2600-smp 258 - brcm,bcm11351-cpu-method 259 - brcm,bcm23550 260 - brcm,bcm2836-smp 261 - brcm,bcm63138 262 - brcm,bcm-nsp-smp 263 - brcm,brahma-b15 264 - marvell,armada-375-smp 265 - marvell,armada-380-smp 266 - marvell,armada-390-smp 267 - marvell,armada-xp-smp 268 - marvell,98dx3236-smp 269 - marvell,mmp3-smp 270 - mediatek,mt6589-smp 271 - mediatek,mt81xx-tz-smp 272 - qcom,gcc-msm8660 273 - qcom,kpss-acc-v1 274 - qcom,kpss-acc-v2 275 - qcom,msm8226-smp 276 - qcom,msm8909-smp 277 # Only valid on ARM 32-bit, see above for ARM v8 64-bit 278 - qcom,msm8916-smp 279 - renesas,apmu 280 - renesas,r9a06g032-smp 281 - rockchip,rk3036-smp 282 - rockchip,rk3066-smp 283 - socionext,milbeaut-m10v-smp 284 - ste,dbx500-smp 285 - ti,am3352 286 - ti,am4372 287 288 cpu-release-addr: 289 oneOf: 290 - $ref: /schemas/types.yaml#/definitions/uint32 291 - $ref: /schemas/types.yaml#/definitions/uint64 292 description: 293 The DT specification defines this as 64-bit always, but some 32-bit Arm 294 systems have used a 32-bit value which must be supported. 295 296 cpu-idle-states: 297 $ref: /schemas/types.yaml#/definitions/phandle-array 298 items: 299 maxItems: 1 300 description: 301 List of phandles to idle state nodes supported by this cpu (see 302 ./idle-states.yaml). 303 304 capacity-dmips-mhz: 305 description: 306 u32 value representing CPU capacity (see ../cpu/cpu-capacity.txt) in 307 DMIPS/MHz, relative to highest capacity-dmips-mhz in the system. 308 309 cci-control-port: true 310 311 dynamic-power-coefficient: 312 $ref: /schemas/types.yaml#/definitions/uint32 313 description: > 314 A u32 value that represents the running time dynamic power coefficient in 315 units of uW/MHz/V^2. The coefficient can either be calculated from power 316 measurements or derived by analysis. 317 318 The dynamic power consumption of the CPU is proportional to the square of 319 the Voltage (V) and the clock frequency (f). The coefficient is used to 320 calculate the dynamic power as below - 321 322 Pdyn = dynamic-power-coefficient * V^2 * f 323 324 where voltage is in V, frequency is in MHz. 325 326 interconnects: 327 minItems: 1 328 maxItems: 3 329 330 nvmem-cells: 331 maxItems: 1 332 333 nvmem-cell-names: 334 const: speed_grade 335 336 performance-domains: 337 maxItems: 1 338 339 power-domains: 340 minItems: 1 341 maxItems: 2 342 343 power-domain-names: 344 description: 345 For PSCI based platforms, the name corresponding to the index of the PSCI 346 PM domain provider, must be "psci". For SCMI based platforms, the name 347 corresponding to the index of an SCMI performance domain provider, must be 348 "perf". 349 minItems: 1 350 maxItems: 2 351 items: 352 enum: [ psci, perf, cpr ] 353 354 resets: 355 maxItems: 1 356 357 arm-supply: 358 deprecated: true 359 description: Use 'cpu-supply' instead 360 361 cpu0-supply: 362 deprecated: true 363 description: Use 'cpu-supply' instead 364 365 mem-supply: true 366 367 proc-supply: 368 deprecated: true 369 description: Use 'cpu-supply' instead 370 371 pu-supply: 372 deprecated: true 373 description: Only for i.MX6Q/DL/SL SoCs. 374 375 soc-supply: 376 deprecated: true 377 description: Only for i.MX6/7 Soc. 378 379 sram-supply: 380 deprecated: true 381 description: Use 'mem-supply' instead 382 383 fsl,soc-operating-points: 384 $ref: /schemas/types.yaml#/definitions/uint32-matrix 385 description: FSL i.MX6 Soc operation-points when change cpu frequency 386 deprecated: true 387 items: 388 items: 389 - description: Frequency in kHz 390 - description: Voltage for OPP in uV 391 392 mediatek,cci: 393 $ref: /schemas/types.yaml#/definitions/phandle 394 description: Link to Mediatek Cache Coherent Interconnect 395 396 edac-enabled: 397 $ref: /schemas/types.yaml#/definitions/flag 398 description: 399 A72 CPUs support Error Detection And Correction (EDAC) on their L1 and 400 L2 caches. This flag marks this function as usable. 401 402 qcom,saw: 403 $ref: /schemas/types.yaml#/definitions/phandle 404 description: 405 Specifies the SAW node associated with this CPU. 406 407 qcom,acc: 408 $ref: /schemas/types.yaml#/definitions/phandle 409 description: 410 Specifies the ACC node associated with this CPU. 411 412 qcom,freq-domain: 413 description: Specifies the QCom CPUFREQ HW associated with the CPU. 414 $ref: /schemas/types.yaml#/definitions/phandle-array 415 maxItems: 1 416 417 rockchip,pmu: 418 $ref: /schemas/types.yaml#/definitions/phandle 419 description: > 420 Specifies the syscon node controlling the cpu core power domains. 421 422 Optional for systems that have an "enable-method" property value of 423 "rockchip,rk3066-smp". While optional, it is the preferred way to get 424 access to the cpu-core power-domains. 425 426 secondary-boot-reg: 427 $ref: /schemas/types.yaml#/definitions/uint32 428 description: > 429 Required for systems that have an "enable-method" property value of 430 "brcm,bcm11351-cpu-method", "brcm,bcm23550" or "brcm,bcm-nsp-smp". 431 432 This includes the following SoCs: 433 BCM11130, BCM11140, BCM11351, BCM28145, BCM28155, BCM21664, BCM23550, 434 BCM58522, BCM58525, BCM58535, BCM58622, BCM58623, BCM58625, BCM88312 435 436 The secondary-boot-reg property is a u32 value that specifies the 437 physical address of the register used to request the ROM holding pen 438 code release a secondary CPU. The value written to the register is 439 formed by encoding the target CPU id into the low bits of the 440 physical start address it should jump to. 441 442 thermal-idle: 443 type: object 444 445allOf: 446 - $ref: /schemas/cpu.yaml# 447 - $ref: /schemas/opp/opp-v1.yaml# 448 - if: 449 not: 450 properties: 451 compatible: 452 contains: 453 const: arm,cortex-a72 454 then: 455 # Allow edac-enabled only for Cortex A72 456 properties: 457 edac-enabled: false 458 459 - if: 460 # If the enable-method property contains one of those values 461 properties: 462 enable-method: 463 contains: 464 enum: 465 - brcm,bcm11351-cpu-method 466 - brcm,bcm23550 467 - brcm,bcm-nsp-smp 468 # and if enable-method is present 469 required: 470 - enable-method 471 then: 472 required: 473 - secondary-boot-reg 474 - if: 475 properties: 476 enable-method: 477 enum: 478 - spin-table 479 - renesas,r9a06g032-smp 480 required: 481 - enable-method 482 then: 483 required: 484 - cpu-release-addr 485 - if: 486 properties: 487 enable-method: 488 enum: 489 - qcom,kpss-acc-v1 490 - qcom,kpss-acc-v2 491 - qcom,msm8226-smp 492 - qcom,msm8916-smp 493 required: 494 - enable-method 495 then: 496 required: 497 - qcom,acc 498 - qcom,saw 499 else: 500 if: 501 # 2 Qualcomm platforms bootloaders need qcom,acc and qcom,saw yet use 502 # "spin-table" or "psci" enable-methods. Disallowing the properties for 503 # all other CPUs is the best we can do as there's not any way to 504 # distinguish these Qualcomm platforms. 505 not: 506 properties: 507 compatible: 508 const: arm,cortex-a53 509 then: 510 properties: 511 qcom,acc: false 512 qcom,saw: false 513 514required: 515 - device_type 516 - reg 517 - compatible 518 519dependencies: 520 rockchip,pmu: [enable-method] 521 522unevaluatedProperties: false 523 524examples: 525 - | 526 cpus { 527 #size-cells = <0>; 528 #address-cells = <1>; 529 530 cpu@0 { 531 device_type = "cpu"; 532 compatible = "arm,cortex-a15"; 533 reg = <0x0>; 534 }; 535 536 cpu@1 { 537 device_type = "cpu"; 538 compatible = "arm,cortex-a15"; 539 reg = <0x1>; 540 }; 541 542 cpu@100 { 543 device_type = "cpu"; 544 compatible = "arm,cortex-a7"; 545 reg = <0x100>; 546 }; 547 548 cpu@101 { 549 device_type = "cpu"; 550 compatible = "arm,cortex-a7"; 551 reg = <0x101>; 552 }; 553 }; 554 555 - | 556 // Example 2 (Cortex-A8 uniprocessor 32-bit system): 557 cpus { 558 #size-cells = <0>; 559 #address-cells = <1>; 560 561 cpu@0 { 562 device_type = "cpu"; 563 compatible = "arm,cortex-a8"; 564 reg = <0x0>; 565 }; 566 }; 567 568 - | 569 // Example 3 (ARM 926EJ-S uniprocessor 32-bit system): 570 cpus { 571 #size-cells = <0>; 572 #address-cells = <1>; 573 574 cpu@0 { 575 device_type = "cpu"; 576 compatible = "arm,arm926ej-s"; 577 reg = <0x0>; 578 }; 579 }; 580 581 - | 582 // Example 4 (ARM Cortex-A57 64-bit system): 583 cpus { 584 #size-cells = <0>; 585 #address-cells = <2>; 586 587 cpu@0 { 588 device_type = "cpu"; 589 compatible = "arm,cortex-a57"; 590 reg = <0x0 0x0>; 591 enable-method = "spin-table"; 592 cpu-release-addr = <0 0x20000000>; 593 }; 594 595 cpu@1 { 596 device_type = "cpu"; 597 compatible = "arm,cortex-a57"; 598 reg = <0x0 0x1>; 599 enable-method = "spin-table"; 600 cpu-release-addr = <0 0x20000000>; 601 }; 602 603 cpu@100 { 604 device_type = "cpu"; 605 compatible = "arm,cortex-a57"; 606 reg = <0x0 0x100>; 607 enable-method = "spin-table"; 608 cpu-release-addr = <0 0x20000000>; 609 }; 610 611 cpu@101 { 612 device_type = "cpu"; 613 compatible = "arm,cortex-a57"; 614 reg = <0x0 0x101>; 615 enable-method = "spin-table"; 616 cpu-release-addr = <0 0x20000000>; 617 }; 618 619 cpu@10000 { 620 device_type = "cpu"; 621 compatible = "arm,cortex-a57"; 622 reg = <0x0 0x10000>; 623 enable-method = "spin-table"; 624 cpu-release-addr = <0 0x20000000>; 625 }; 626 627 cpu@10001 { 628 device_type = "cpu"; 629 compatible = "arm,cortex-a57"; 630 reg = <0x0 0x10001>; 631 enable-method = "spin-table"; 632 cpu-release-addr = <0 0x20000000>; 633 }; 634 635 cpu@10100 { 636 device_type = "cpu"; 637 compatible = "arm,cortex-a57"; 638 reg = <0x0 0x10100>; 639 enable-method = "spin-table"; 640 cpu-release-addr = <0 0x20000000>; 641 }; 642 643 cpu@10101 { 644 device_type = "cpu"; 645 compatible = "arm,cortex-a57"; 646 reg = <0x0 0x10101>; 647 enable-method = "spin-table"; 648 cpu-release-addr = <0 0x20000000>; 649 }; 650 651 cpu@100000000 { 652 device_type = "cpu"; 653 compatible = "arm,cortex-a57"; 654 reg = <0x1 0x0>; 655 enable-method = "spin-table"; 656 cpu-release-addr = <0 0x20000000>; 657 }; 658 659 cpu@100000001 { 660 device_type = "cpu"; 661 compatible = "arm,cortex-a57"; 662 reg = <0x1 0x1>; 663 enable-method = "spin-table"; 664 cpu-release-addr = <0 0x20000000>; 665 }; 666 667 cpu@100000100 { 668 device_type = "cpu"; 669 compatible = "arm,cortex-a57"; 670 reg = <0x1 0x100>; 671 enable-method = "spin-table"; 672 cpu-release-addr = <0 0x20000000>; 673 }; 674 675 cpu@100000101 { 676 device_type = "cpu"; 677 compatible = "arm,cortex-a57"; 678 reg = <0x1 0x101>; 679 enable-method = "spin-table"; 680 cpu-release-addr = <0 0x20000000>; 681 }; 682 683 cpu@100010000 { 684 device_type = "cpu"; 685 compatible = "arm,cortex-a57"; 686 reg = <0x1 0x10000>; 687 enable-method = "spin-table"; 688 cpu-release-addr = <0 0x20000000>; 689 }; 690 691 cpu@100010001 { 692 device_type = "cpu"; 693 compatible = "arm,cortex-a57"; 694 reg = <0x1 0x10001>; 695 enable-method = "spin-table"; 696 cpu-release-addr = <0 0x20000000>; 697 }; 698 699 cpu@100010100 { 700 device_type = "cpu"; 701 compatible = "arm,cortex-a57"; 702 reg = <0x1 0x10100>; 703 enable-method = "spin-table"; 704 cpu-release-addr = <0 0x20000000>; 705 }; 706 707 cpu@100010101 { 708 device_type = "cpu"; 709 compatible = "arm,cortex-a57"; 710 reg = <0x1 0x10101>; 711 enable-method = "spin-table"; 712 cpu-release-addr = <0 0x20000000>; 713 }; 714 }; 715... 716