1# SPDX-License-Identifier: GPL-2.0 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/arm/cpus.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: ARM CPUs 8 9maintainers: 10 - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> 11 12description: |+ 13 The device tree allows to describe the layout of CPUs in a system through 14 the "cpus" node, which in turn contains a number of subnodes (ie "cpu") 15 defining properties for every cpu. 16 17 Bindings for CPU nodes follow the Devicetree Specification, available from: 18 19 https://www.devicetree.org/specifications/ 20 21 with updates for 32-bit and 64-bit ARM systems provided in this document. 22 23 ================================ 24 Convention used in this document 25 ================================ 26 27 This document follows the conventions described in the Devicetree 28 Specification, with the addition: 29 30 - square brackets define bitfields, eg reg[7:0] value of the bitfield in 31 the reg property contained in bits 7 down to 0 32 33 ===================================== 34 cpus and cpu node bindings definition 35 ===================================== 36 37 The ARM architecture, in accordance with the Devicetree Specification, 38 requires the cpus and cpu nodes to be present and contain the properties 39 described below. 40 41properties: 42 reg: 43 maxItems: 1 44 description: | 45 Usage and definition depend on ARM architecture version and 46 configuration: 47 48 On uniprocessor ARM architectures previous to v7 49 this property is required and must be set to 0. 50 51 On ARM 11 MPcore based systems this property is 52 required and matches the CPUID[11:0] register bits. 53 54 Bits [11:0] in the reg cell must be set to 55 bits [11:0] in CPU ID register. 56 57 All other bits in the reg cell must be set to 0. 58 59 On 32-bit ARM v7 or later systems this property is 60 required and matches the CPU MPIDR[23:0] register 61 bits. 62 63 Bits [23:0] in the reg cell must be set to 64 bits [23:0] in MPIDR. 65 66 All other bits in the reg cell must be set to 0. 67 68 On ARM v8 64-bit systems this property is required 69 and matches the MPIDR_EL1 register affinity bits. 70 71 * If cpus node's #address-cells property is set to 2 72 73 The first reg cell bits [7:0] must be set to 74 bits [39:32] of MPIDR_EL1. 75 76 The second reg cell bits [23:0] must be set to 77 bits [23:0] of MPIDR_EL1. 78 79 * If cpus node's #address-cells property is set to 1 80 81 The reg cell bits [23:0] must be set to bits [23:0] 82 of MPIDR_EL1. 83 84 All other bits in the reg cells must be set to 0. 85 86 compatible: 87 enum: 88 - apple,avalanche 89 - apple,blizzard 90 - apple,icestorm 91 - apple,firestorm 92 - arm,arm710t 93 - arm,arm720t 94 - arm,arm740t 95 - arm,arm7ej-s 96 - arm,arm7tdmi 97 - arm,arm7tdmi-s 98 - arm,arm9es 99 - arm,arm9ej-s 100 - arm,arm920t 101 - arm,arm922t 102 - arm,arm925 103 - arm,arm926e-s 104 - arm,arm926ej-s 105 - arm,arm940t 106 - arm,arm946e-s 107 - arm,arm966e-s 108 - arm,arm968e-s 109 - arm,arm9tdmi 110 - arm,arm1020e 111 - arm,arm1020t 112 - arm,arm1022e 113 - arm,arm1026ej-s 114 - arm,arm1136j-s 115 - arm,arm1136jf-s 116 - arm,arm1156t2-s 117 - arm,arm1156t2f-s 118 - arm,arm1176jzf 119 - arm,arm1176jz-s 120 - arm,arm1176jzf-s 121 - arm,arm11mpcore 122 - arm,armv8 # Only for s/w models 123 - arm,cortex-a5 124 - arm,cortex-a7 125 - arm,cortex-a8 126 - arm,cortex-a9 127 - arm,cortex-a12 128 - arm,cortex-a15 129 - arm,cortex-a17 130 - arm,cortex-a32 131 - arm,cortex-a34 132 - arm,cortex-a35 133 - arm,cortex-a53 134 - arm,cortex-a55 135 - arm,cortex-a57 136 - arm,cortex-a65 137 - arm,cortex-a72 138 - arm,cortex-a73 139 - arm,cortex-a75 140 - arm,cortex-a76 141 - arm,cortex-a77 142 - arm,cortex-a78 143 - arm,cortex-a78ae 144 - arm,cortex-a78c 145 - arm,cortex-a510 146 - arm,cortex-a520 147 - arm,cortex-a710 148 - arm,cortex-a715 149 - arm,cortex-a720 150 - arm,cortex-m0 151 - arm,cortex-m0+ 152 - arm,cortex-m1 153 - arm,cortex-m3 154 - arm,cortex-m4 155 - arm,cortex-r4 156 - arm,cortex-r5 157 - arm,cortex-r7 158 - arm,cortex-r52 159 - arm,cortex-x1 160 - arm,cortex-x1c 161 - arm,cortex-x2 162 - arm,cortex-x3 163 - arm,cortex-x4 164 - arm,neoverse-e1 165 - arm,neoverse-n1 166 - arm,neoverse-n2 167 - arm,neoverse-v1 168 - brcm,brahma-b15 169 - brcm,brahma-b53 170 - brcm,vulcan 171 - cavium,thunder 172 - cavium,thunder2 173 - faraday,fa526 174 - intel,sa110 175 - intel,sa1100 176 - marvell,feroceon 177 - marvell,mohawk 178 - marvell,pj4a 179 - marvell,pj4b 180 - marvell,sheeva-v5 181 - marvell,sheeva-v7 182 - nvidia,tegra132-denver 183 - nvidia,tegra186-denver 184 - nvidia,tegra194-carmel 185 - qcom,krait 186 - qcom,kryo 187 - qcom,kryo240 188 - qcom,kryo250 189 - qcom,kryo260 190 - qcom,kryo280 191 - qcom,kryo360 192 - qcom,kryo385 193 - qcom,kryo468 194 - qcom,kryo485 195 - qcom,kryo560 196 - qcom,kryo570 197 - qcom,kryo660 198 - qcom,kryo685 199 - qcom,kryo780 200 - qcom,scorpion 201 202 enable-method: 203 $ref: /schemas/types.yaml#/definitions/string 204 oneOf: 205 # On ARM v8 64-bit this property is required 206 - enum: 207 - psci 208 - spin-table 209 # On ARM 32-bit systems this property is optional 210 - enum: 211 - actions,s500-smp 212 - allwinner,sun6i-a31 213 - allwinner,sun8i-a23 214 - allwinner,sun9i-a80-smp 215 - allwinner,sun8i-a83t-smp 216 - amlogic,meson8-smp 217 - amlogic,meson8b-smp 218 - arm,realview-smp 219 - aspeed,ast2600-smp 220 - brcm,bcm11351-cpu-method 221 - brcm,bcm23550 222 - brcm,bcm2836-smp 223 - brcm,bcm63138 224 - brcm,bcm-nsp-smp 225 - brcm,brahma-b15 226 - marvell,armada-375-smp 227 - marvell,armada-380-smp 228 - marvell,armada-390-smp 229 - marvell,armada-xp-smp 230 - marvell,98dx3236-smp 231 - marvell,mmp3-smp 232 - mediatek,mt6589-smp 233 - mediatek,mt81xx-tz-smp 234 - qcom,gcc-msm8660 235 - qcom,kpss-acc-v1 236 - qcom,kpss-acc-v2 237 - qcom,msm8226-smp 238 - qcom,msm8909-smp 239 # Only valid on ARM 32-bit, see above for ARM v8 64-bit 240 - qcom,msm8916-smp 241 - renesas,apmu 242 - renesas,r9a06g032-smp 243 - rockchip,rk3036-smp 244 - rockchip,rk3066-smp 245 - socionext,milbeaut-m10v-smp 246 - ste,dbx500-smp 247 - ti,am3352 248 - ti,am4372 249 250 cpu-release-addr: 251 oneOf: 252 - $ref: /schemas/types.yaml#/definitions/uint32 253 - $ref: /schemas/types.yaml#/definitions/uint64 254 description: 255 The DT specification defines this as 64-bit always, but some 32-bit Arm 256 systems have used a 32-bit value which must be supported. 257 Required for systems that have an "enable-method" 258 property value of "spin-table". 259 260 cpu-idle-states: 261 $ref: /schemas/types.yaml#/definitions/phandle-array 262 items: 263 maxItems: 1 264 description: | 265 List of phandles to idle state nodes supported 266 by this cpu (see ./idle-states.yaml). 267 268 capacity-dmips-mhz: 269 description: 270 u32 value representing CPU capacity (see ../cpu/cpu-capacity.txt) in 271 DMIPS/MHz, relative to highest capacity-dmips-mhz 272 in the system. 273 274 cci-control-port: true 275 276 dynamic-power-coefficient: 277 $ref: /schemas/types.yaml#/definitions/uint32 278 description: 279 A u32 value that represents the running time dynamic 280 power coefficient in units of uW/MHz/V^2. The 281 coefficient can either be calculated from power 282 measurements or derived by analysis. 283 284 The dynamic power consumption of the CPU is 285 proportional to the square of the Voltage (V) and 286 the clock frequency (f). The coefficient is used to 287 calculate the dynamic power as below - 288 289 Pdyn = dynamic-power-coefficient * V^2 * f 290 291 where voltage is in V, frequency is in MHz. 292 293 performance-domains: 294 maxItems: 1 295 description: 296 List of phandles and performance domain specifiers, as defined by 297 bindings of the performance domain provider. See also 298 dvfs/performance-domain.yaml. 299 300 power-domains: 301 description: 302 List of phandles and PM domain specifiers, as defined by bindings of the 303 PM domain provider (see also ../power_domain.txt). 304 305 power-domain-names: 306 description: 307 A list of power domain name strings sorted in the same order as the 308 power-domains property. 309 310 For PSCI based platforms, the name corresponding to the index of the PSCI 311 PM domain provider, must be "psci". 312 313 qcom,saw: 314 $ref: /schemas/types.yaml#/definitions/phandle 315 description: | 316 Specifies the SAW* node associated with this CPU. 317 318 Required for systems that have an "enable-method" property 319 value of "qcom,kpss-acc-v1" or "qcom,kpss-acc-v2" 320 321 * arm/msm/qcom,saw2.txt 322 323 qcom,acc: 324 $ref: /schemas/types.yaml#/definitions/phandle 325 description: | 326 Specifies the ACC* node associated with this CPU. 327 328 Required for systems that have an "enable-method" property 329 value of "qcom,kpss-acc-v1", "qcom,kpss-acc-v2", "qcom,msm8226-smp" or 330 "qcom,msm8916-smp". 331 332 * arm/msm/qcom,kpss-acc.txt 333 334 rockchip,pmu: 335 $ref: /schemas/types.yaml#/definitions/phandle 336 description: | 337 Specifies the syscon node controlling the cpu core power domains. 338 339 Optional for systems that have an "enable-method" 340 property value of "rockchip,rk3066-smp" 341 While optional, it is the preferred way to get access to 342 the cpu-core power-domains. 343 344 secondary-boot-reg: 345 $ref: /schemas/types.yaml#/definitions/uint32 346 description: | 347 Required for systems that have an "enable-method" property value of 348 "brcm,bcm11351-cpu-method", "brcm,bcm23550" or "brcm,bcm-nsp-smp". 349 350 This includes the following SoCs: | 351 BCM11130, BCM11140, BCM11351, BCM28145, BCM28155, BCM21664, BCM23550 352 BCM58522, BCM58525, BCM58535, BCM58622, BCM58623, BCM58625, BCM88312 353 354 The secondary-boot-reg property is a u32 value that specifies the 355 physical address of the register used to request the ROM holding pen 356 code release a secondary CPU. The value written to the register is 357 formed by encoding the target CPU id into the low bits of the 358 physical start address it should jump to. 359 360if: 361 # If the enable-method property contains one of those values 362 properties: 363 enable-method: 364 contains: 365 enum: 366 - brcm,bcm11351-cpu-method 367 - brcm,bcm23550 368 - brcm,bcm-nsp-smp 369 # and if enable-method is present 370 required: 371 - enable-method 372 373then: 374 required: 375 - secondary-boot-reg 376 377required: 378 - device_type 379 - reg 380 - compatible 381 382dependencies: 383 rockchip,pmu: [enable-method] 384 385additionalProperties: true 386 387examples: 388 - | 389 cpus { 390 #size-cells = <0>; 391 #address-cells = <1>; 392 393 cpu@0 { 394 device_type = "cpu"; 395 compatible = "arm,cortex-a15"; 396 reg = <0x0>; 397 }; 398 399 cpu@1 { 400 device_type = "cpu"; 401 compatible = "arm,cortex-a15"; 402 reg = <0x1>; 403 }; 404 405 cpu@100 { 406 device_type = "cpu"; 407 compatible = "arm,cortex-a7"; 408 reg = <0x100>; 409 }; 410 411 cpu@101 { 412 device_type = "cpu"; 413 compatible = "arm,cortex-a7"; 414 reg = <0x101>; 415 }; 416 }; 417 418 - | 419 // Example 2 (Cortex-A8 uniprocessor 32-bit system): 420 cpus { 421 #size-cells = <0>; 422 #address-cells = <1>; 423 424 cpu@0 { 425 device_type = "cpu"; 426 compatible = "arm,cortex-a8"; 427 reg = <0x0>; 428 }; 429 }; 430 431 - | 432 // Example 3 (ARM 926EJ-S uniprocessor 32-bit system): 433 cpus { 434 #size-cells = <0>; 435 #address-cells = <1>; 436 437 cpu@0 { 438 device_type = "cpu"; 439 compatible = "arm,arm926ej-s"; 440 reg = <0x0>; 441 }; 442 }; 443 444 - | 445 // Example 4 (ARM Cortex-A57 64-bit system): 446 cpus { 447 #size-cells = <0>; 448 #address-cells = <2>; 449 450 cpu@0 { 451 device_type = "cpu"; 452 compatible = "arm,cortex-a57"; 453 reg = <0x0 0x0>; 454 enable-method = "spin-table"; 455 cpu-release-addr = <0 0x20000000>; 456 }; 457 458 cpu@1 { 459 device_type = "cpu"; 460 compatible = "arm,cortex-a57"; 461 reg = <0x0 0x1>; 462 enable-method = "spin-table"; 463 cpu-release-addr = <0 0x20000000>; 464 }; 465 466 cpu@100 { 467 device_type = "cpu"; 468 compatible = "arm,cortex-a57"; 469 reg = <0x0 0x100>; 470 enable-method = "spin-table"; 471 cpu-release-addr = <0 0x20000000>; 472 }; 473 474 cpu@101 { 475 device_type = "cpu"; 476 compatible = "arm,cortex-a57"; 477 reg = <0x0 0x101>; 478 enable-method = "spin-table"; 479 cpu-release-addr = <0 0x20000000>; 480 }; 481 482 cpu@10000 { 483 device_type = "cpu"; 484 compatible = "arm,cortex-a57"; 485 reg = <0x0 0x10000>; 486 enable-method = "spin-table"; 487 cpu-release-addr = <0 0x20000000>; 488 }; 489 490 cpu@10001 { 491 device_type = "cpu"; 492 compatible = "arm,cortex-a57"; 493 reg = <0x0 0x10001>; 494 enable-method = "spin-table"; 495 cpu-release-addr = <0 0x20000000>; 496 }; 497 498 cpu@10100 { 499 device_type = "cpu"; 500 compatible = "arm,cortex-a57"; 501 reg = <0x0 0x10100>; 502 enable-method = "spin-table"; 503 cpu-release-addr = <0 0x20000000>; 504 }; 505 506 cpu@10101 { 507 device_type = "cpu"; 508 compatible = "arm,cortex-a57"; 509 reg = <0x0 0x10101>; 510 enable-method = "spin-table"; 511 cpu-release-addr = <0 0x20000000>; 512 }; 513 514 cpu@100000000 { 515 device_type = "cpu"; 516 compatible = "arm,cortex-a57"; 517 reg = <0x1 0x0>; 518 enable-method = "spin-table"; 519 cpu-release-addr = <0 0x20000000>; 520 }; 521 522 cpu@100000001 { 523 device_type = "cpu"; 524 compatible = "arm,cortex-a57"; 525 reg = <0x1 0x1>; 526 enable-method = "spin-table"; 527 cpu-release-addr = <0 0x20000000>; 528 }; 529 530 cpu@100000100 { 531 device_type = "cpu"; 532 compatible = "arm,cortex-a57"; 533 reg = <0x1 0x100>; 534 enable-method = "spin-table"; 535 cpu-release-addr = <0 0x20000000>; 536 }; 537 538 cpu@100000101 { 539 device_type = "cpu"; 540 compatible = "arm,cortex-a57"; 541 reg = <0x1 0x101>; 542 enable-method = "spin-table"; 543 cpu-release-addr = <0 0x20000000>; 544 }; 545 546 cpu@100010000 { 547 device_type = "cpu"; 548 compatible = "arm,cortex-a57"; 549 reg = <0x1 0x10000>; 550 enable-method = "spin-table"; 551 cpu-release-addr = <0 0x20000000>; 552 }; 553 554 cpu@100010001 { 555 device_type = "cpu"; 556 compatible = "arm,cortex-a57"; 557 reg = <0x1 0x10001>; 558 enable-method = "spin-table"; 559 cpu-release-addr = <0 0x20000000>; 560 }; 561 562 cpu@100010100 { 563 device_type = "cpu"; 564 compatible = "arm,cortex-a57"; 565 reg = <0x1 0x10100>; 566 enable-method = "spin-table"; 567 cpu-release-addr = <0 0x20000000>; 568 }; 569 570 cpu@100010101 { 571 device_type = "cpu"; 572 compatible = "arm,cortex-a57"; 573 reg = <0x1 0x10101>; 574 enable-method = "spin-table"; 575 cpu-release-addr = <0 0x20000000>; 576 }; 577 }; 578... 579