1# SPDX-License-Identifier: GPL-2.0 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/arm/cpus.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: ARM CPUs 8 9maintainers: 10 - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> 11 12description: |+ 13 The device tree allows to describe the layout of CPUs in a system through 14 the "cpus" node, which in turn contains a number of subnodes (ie "cpu") 15 defining properties for every cpu. 16 17 Bindings for CPU nodes follow the Devicetree Specification, available from: 18 19 https://www.devicetree.org/specifications/ 20 21 with updates for 32-bit and 64-bit ARM systems provided in this document. 22 23 ================================ 24 Convention used in this document 25 ================================ 26 27 This document follows the conventions described in the Devicetree 28 Specification, with the addition: 29 30 - square brackets define bitfields, eg reg[7:0] value of the bitfield in 31 the reg property contained in bits 7 down to 0 32 33 ===================================== 34 cpus and cpu node bindings definition 35 ===================================== 36 37 The ARM architecture, in accordance with the Devicetree Specification, 38 requires the cpus and cpu nodes to be present and contain the properties 39 described below. 40 41properties: 42 reg: 43 maxItems: 1 44 description: | 45 Usage and definition depend on ARM architecture version and 46 configuration: 47 48 On uniprocessor ARM architectures previous to v7 49 this property is required and must be set to 0. 50 51 On ARM 11 MPcore based systems this property is 52 required and matches the CPUID[11:0] register bits. 53 54 Bits [11:0] in the reg cell must be set to 55 bits [11:0] in CPU ID register. 56 57 All other bits in the reg cell must be set to 0. 58 59 On 32-bit ARM v7 or later systems this property is 60 required and matches the CPU MPIDR[23:0] register 61 bits. 62 63 Bits [23:0] in the reg cell must be set to 64 bits [23:0] in MPIDR. 65 66 All other bits in the reg cell must be set to 0. 67 68 On ARM v8 64-bit systems this property is required 69 and matches the MPIDR_EL1 register affinity bits. 70 71 * If cpus node's #address-cells property is set to 2 72 73 The first reg cell bits [7:0] must be set to 74 bits [39:32] of MPIDR_EL1. 75 76 The second reg cell bits [23:0] must be set to 77 bits [23:0] of MPIDR_EL1. 78 79 * If cpus node's #address-cells property is set to 1 80 81 The reg cell bits [23:0] must be set to bits [23:0] 82 of MPIDR_EL1. 83 84 All other bits in the reg cells must be set to 0. 85 86 compatible: 87 enum: 88 - apple,avalanche 89 - apple,blizzard 90 - apple,cyclone 91 - apple,firestorm 92 - apple,hurricane-zephyr 93 - apple,icestorm 94 - apple,mistral 95 - apple,monsoon 96 - apple,twister 97 - apple,typhoon 98 - arm,arm710t 99 - arm,arm720t 100 - arm,arm740t 101 - arm,arm7ej-s 102 - arm,arm7tdmi 103 - arm,arm7tdmi-s 104 - arm,arm9es 105 - arm,arm9ej-s 106 - arm,arm920t 107 - arm,arm922t 108 - arm,arm925 109 - arm,arm926e-s 110 - arm,arm926ej-s 111 - arm,arm940t 112 - arm,arm946e-s 113 - arm,arm966e-s 114 - arm,arm968e-s 115 - arm,arm9tdmi 116 - arm,arm1020e 117 - arm,arm1020t 118 - arm,arm1022e 119 - arm,arm1026ej-s 120 - arm,arm1136j-s 121 - arm,arm1136jf-s 122 - arm,arm1156t2-s 123 - arm,arm1156t2f-s 124 - arm,arm1176jzf 125 - arm,arm1176jz-s 126 - arm,arm1176jzf-s 127 - arm,arm11mpcore 128 - arm,armv8 # Only for s/w models 129 - arm,cortex-a5 130 - arm,cortex-a7 131 - arm,cortex-a8 132 - arm,cortex-a9 133 - arm,cortex-a12 134 - arm,cortex-a15 135 - arm,cortex-a17 136 - arm,cortex-a32 137 - arm,cortex-a34 138 - arm,cortex-a35 139 - arm,cortex-a53 140 - arm,cortex-a55 141 - arm,cortex-a57 142 - arm,cortex-a65 143 - arm,cortex-a72 144 - arm,cortex-a73 145 - arm,cortex-a75 146 - arm,cortex-a76 147 - arm,cortex-a77 148 - arm,cortex-a78 149 - arm,cortex-a78ae 150 - arm,cortex-a78c 151 - arm,cortex-a510 152 - arm,cortex-a520 153 - arm,cortex-a710 154 - arm,cortex-a715 155 - arm,cortex-a720 156 - arm,cortex-a725 157 - arm,cortex-m0 158 - arm,cortex-m0+ 159 - arm,cortex-m1 160 - arm,cortex-m3 161 - arm,cortex-m4 162 - arm,cortex-r4 163 - arm,cortex-r5 164 - arm,cortex-r7 165 - arm,cortex-r52 166 - arm,cortex-x1 167 - arm,cortex-x1c 168 - arm,cortex-x2 169 - arm,cortex-x3 170 - arm,cortex-x4 171 - arm,cortex-x925 172 - arm,neoverse-e1 173 - arm,neoverse-n1 174 - arm,neoverse-n2 175 - arm,neoverse-n3 176 - arm,neoverse-v1 177 - arm,neoverse-v2 178 - arm,neoverse-v3 179 - arm,neoverse-v3ae 180 - brcm,brahma-b15 181 - brcm,brahma-b53 182 - brcm,vulcan 183 - cavium,thunder 184 - cavium,thunder2 185 - faraday,fa526 186 - intel,sa110 187 - intel,sa1100 188 - marvell,feroceon 189 - marvell,mohawk 190 - marvell,pj4a 191 - marvell,pj4b 192 - marvell,sheeva-v5 193 - marvell,sheeva-v7 194 - nvidia,tegra132-denver 195 - nvidia,tegra186-denver 196 - nvidia,tegra194-carmel 197 - qcom,krait 198 - qcom,kryo 199 - qcom,kryo240 200 - qcom,kryo250 201 - qcom,kryo260 202 - qcom,kryo280 203 - qcom,kryo360 204 - qcom,kryo385 205 - qcom,kryo465 206 - qcom,kryo468 207 - qcom,kryo485 208 - qcom,kryo560 209 - qcom,kryo570 210 - qcom,kryo660 211 - qcom,kryo670 212 - qcom,kryo685 213 - qcom,kryo780 214 - qcom,oryon 215 - qcom,scorpion 216 - samsung,mongoose-m2 217 - samsung,mongoose-m3 218 - samsung,mongoose-m5 219 220 enable-method: 221 $ref: /schemas/types.yaml#/definitions/string 222 oneOf: 223 # On ARM v8 64-bit this property is required 224 - enum: 225 - psci 226 - spin-table 227 # On ARM 32-bit systems this property is optional 228 - enum: 229 - actions,s500-smp 230 - allwinner,sun6i-a31 231 - allwinner,sun8i-a23 232 - allwinner,sun9i-a80-smp 233 - allwinner,sun8i-a83t-smp 234 - amlogic,meson8-smp 235 - amlogic,meson8b-smp 236 - arm,realview-smp 237 - aspeed,ast2600-smp 238 - brcm,bcm11351-cpu-method 239 - brcm,bcm23550 240 - brcm,bcm2836-smp 241 - brcm,bcm63138 242 - brcm,bcm-nsp-smp 243 - brcm,brahma-b15 244 - marvell,armada-375-smp 245 - marvell,armada-380-smp 246 - marvell,armada-390-smp 247 - marvell,armada-xp-smp 248 - marvell,98dx3236-smp 249 - marvell,mmp3-smp 250 - mediatek,mt6589-smp 251 - mediatek,mt81xx-tz-smp 252 - qcom,gcc-msm8660 253 - qcom,kpss-acc-v1 254 - qcom,kpss-acc-v2 255 - qcom,msm8226-smp 256 - qcom,msm8909-smp 257 # Only valid on ARM 32-bit, see above for ARM v8 64-bit 258 - qcom,msm8916-smp 259 - renesas,apmu 260 - renesas,r9a06g032-smp 261 - rockchip,rk3036-smp 262 - rockchip,rk3066-smp 263 - socionext,milbeaut-m10v-smp 264 - ste,dbx500-smp 265 - ti,am3352 266 - ti,am4372 267 268 cpu-release-addr: 269 oneOf: 270 - $ref: /schemas/types.yaml#/definitions/uint32 271 - $ref: /schemas/types.yaml#/definitions/uint64 272 description: 273 The DT specification defines this as 64-bit always, but some 32-bit Arm 274 systems have used a 32-bit value which must be supported. 275 Required for systems that have an "enable-method" 276 property value of "spin-table". 277 278 cpu-idle-states: 279 $ref: /schemas/types.yaml#/definitions/phandle-array 280 items: 281 maxItems: 1 282 description: | 283 List of phandles to idle state nodes supported 284 by this cpu (see ./idle-states.yaml). 285 286 capacity-dmips-mhz: 287 description: 288 u32 value representing CPU capacity (see ../cpu/cpu-capacity.txt) in 289 DMIPS/MHz, relative to highest capacity-dmips-mhz 290 in the system. 291 292 cci-control-port: true 293 294 dynamic-power-coefficient: 295 $ref: /schemas/types.yaml#/definitions/uint32 296 description: 297 A u32 value that represents the running time dynamic 298 power coefficient in units of uW/MHz/V^2. The 299 coefficient can either be calculated from power 300 measurements or derived by analysis. 301 302 The dynamic power consumption of the CPU is 303 proportional to the square of the Voltage (V) and 304 the clock frequency (f). The coefficient is used to 305 calculate the dynamic power as below - 306 307 Pdyn = dynamic-power-coefficient * V^2 * f 308 309 where voltage is in V, frequency is in MHz. 310 311 performance-domains: 312 maxItems: 1 313 description: 314 List of phandles and performance domain specifiers, as defined by 315 bindings of the performance domain provider. See also 316 dvfs/performance-domain.yaml. 317 318 power-domains: 319 description: 320 List of phandles and PM domain specifiers, as defined by bindings of the 321 PM domain provider (see also ../power_domain.txt). 322 323 power-domain-names: 324 description: 325 A list of power domain name strings sorted in the same order as the 326 power-domains property. 327 328 For PSCI based platforms, the name corresponding to the index of the PSCI 329 PM domain provider, must be "psci". For SCMI based platforms, the name 330 corresponding to the index of an SCMI performance domain provider, must be 331 "perf". 332 333 qcom,saw: 334 $ref: /schemas/types.yaml#/definitions/phandle 335 description: | 336 Specifies the SAW* node associated with this CPU. 337 338 Required for systems that have an "enable-method" property 339 value of "qcom,kpss-acc-v1" or "qcom,kpss-acc-v2" 340 341 * arm/msm/qcom,saw2.txt 342 343 qcom,acc: 344 $ref: /schemas/types.yaml#/definitions/phandle 345 description: | 346 Specifies the ACC* node associated with this CPU. 347 348 Required for systems that have an "enable-method" property 349 value of "qcom,kpss-acc-v1", "qcom,kpss-acc-v2", "qcom,msm8226-smp" or 350 "qcom,msm8916-smp". 351 352 * arm/msm/qcom,kpss-acc.txt 353 354 rockchip,pmu: 355 $ref: /schemas/types.yaml#/definitions/phandle 356 description: | 357 Specifies the syscon node controlling the cpu core power domains. 358 359 Optional for systems that have an "enable-method" 360 property value of "rockchip,rk3066-smp" 361 While optional, it is the preferred way to get access to 362 the cpu-core power-domains. 363 364 secondary-boot-reg: 365 $ref: /schemas/types.yaml#/definitions/uint32 366 description: | 367 Required for systems that have an "enable-method" property value of 368 "brcm,bcm11351-cpu-method", "brcm,bcm23550" or "brcm,bcm-nsp-smp". 369 370 This includes the following SoCs: | 371 BCM11130, BCM11140, BCM11351, BCM28145, BCM28155, BCM21664, BCM23550 372 BCM58522, BCM58525, BCM58535, BCM58622, BCM58623, BCM58625, BCM88312 373 374 The secondary-boot-reg property is a u32 value that specifies the 375 physical address of the register used to request the ROM holding pen 376 code release a secondary CPU. The value written to the register is 377 formed by encoding the target CPU id into the low bits of the 378 physical start address it should jump to. 379 380if: 381 # If the enable-method property contains one of those values 382 properties: 383 enable-method: 384 contains: 385 enum: 386 - brcm,bcm11351-cpu-method 387 - brcm,bcm23550 388 - brcm,bcm-nsp-smp 389 # and if enable-method is present 390 required: 391 - enable-method 392 393then: 394 required: 395 - secondary-boot-reg 396 397required: 398 - device_type 399 - reg 400 - compatible 401 402dependencies: 403 rockchip,pmu: [enable-method] 404 405additionalProperties: true 406 407examples: 408 - | 409 cpus { 410 #size-cells = <0>; 411 #address-cells = <1>; 412 413 cpu@0 { 414 device_type = "cpu"; 415 compatible = "arm,cortex-a15"; 416 reg = <0x0>; 417 }; 418 419 cpu@1 { 420 device_type = "cpu"; 421 compatible = "arm,cortex-a15"; 422 reg = <0x1>; 423 }; 424 425 cpu@100 { 426 device_type = "cpu"; 427 compatible = "arm,cortex-a7"; 428 reg = <0x100>; 429 }; 430 431 cpu@101 { 432 device_type = "cpu"; 433 compatible = "arm,cortex-a7"; 434 reg = <0x101>; 435 }; 436 }; 437 438 - | 439 // Example 2 (Cortex-A8 uniprocessor 32-bit system): 440 cpus { 441 #size-cells = <0>; 442 #address-cells = <1>; 443 444 cpu@0 { 445 device_type = "cpu"; 446 compatible = "arm,cortex-a8"; 447 reg = <0x0>; 448 }; 449 }; 450 451 - | 452 // Example 3 (ARM 926EJ-S uniprocessor 32-bit system): 453 cpus { 454 #size-cells = <0>; 455 #address-cells = <1>; 456 457 cpu@0 { 458 device_type = "cpu"; 459 compatible = "arm,arm926ej-s"; 460 reg = <0x0>; 461 }; 462 }; 463 464 - | 465 // Example 4 (ARM Cortex-A57 64-bit system): 466 cpus { 467 #size-cells = <0>; 468 #address-cells = <2>; 469 470 cpu@0 { 471 device_type = "cpu"; 472 compatible = "arm,cortex-a57"; 473 reg = <0x0 0x0>; 474 enable-method = "spin-table"; 475 cpu-release-addr = <0 0x20000000>; 476 }; 477 478 cpu@1 { 479 device_type = "cpu"; 480 compatible = "arm,cortex-a57"; 481 reg = <0x0 0x1>; 482 enable-method = "spin-table"; 483 cpu-release-addr = <0 0x20000000>; 484 }; 485 486 cpu@100 { 487 device_type = "cpu"; 488 compatible = "arm,cortex-a57"; 489 reg = <0x0 0x100>; 490 enable-method = "spin-table"; 491 cpu-release-addr = <0 0x20000000>; 492 }; 493 494 cpu@101 { 495 device_type = "cpu"; 496 compatible = "arm,cortex-a57"; 497 reg = <0x0 0x101>; 498 enable-method = "spin-table"; 499 cpu-release-addr = <0 0x20000000>; 500 }; 501 502 cpu@10000 { 503 device_type = "cpu"; 504 compatible = "arm,cortex-a57"; 505 reg = <0x0 0x10000>; 506 enable-method = "spin-table"; 507 cpu-release-addr = <0 0x20000000>; 508 }; 509 510 cpu@10001 { 511 device_type = "cpu"; 512 compatible = "arm,cortex-a57"; 513 reg = <0x0 0x10001>; 514 enable-method = "spin-table"; 515 cpu-release-addr = <0 0x20000000>; 516 }; 517 518 cpu@10100 { 519 device_type = "cpu"; 520 compatible = "arm,cortex-a57"; 521 reg = <0x0 0x10100>; 522 enable-method = "spin-table"; 523 cpu-release-addr = <0 0x20000000>; 524 }; 525 526 cpu@10101 { 527 device_type = "cpu"; 528 compatible = "arm,cortex-a57"; 529 reg = <0x0 0x10101>; 530 enable-method = "spin-table"; 531 cpu-release-addr = <0 0x20000000>; 532 }; 533 534 cpu@100000000 { 535 device_type = "cpu"; 536 compatible = "arm,cortex-a57"; 537 reg = <0x1 0x0>; 538 enable-method = "spin-table"; 539 cpu-release-addr = <0 0x20000000>; 540 }; 541 542 cpu@100000001 { 543 device_type = "cpu"; 544 compatible = "arm,cortex-a57"; 545 reg = <0x1 0x1>; 546 enable-method = "spin-table"; 547 cpu-release-addr = <0 0x20000000>; 548 }; 549 550 cpu@100000100 { 551 device_type = "cpu"; 552 compatible = "arm,cortex-a57"; 553 reg = <0x1 0x100>; 554 enable-method = "spin-table"; 555 cpu-release-addr = <0 0x20000000>; 556 }; 557 558 cpu@100000101 { 559 device_type = "cpu"; 560 compatible = "arm,cortex-a57"; 561 reg = <0x1 0x101>; 562 enable-method = "spin-table"; 563 cpu-release-addr = <0 0x20000000>; 564 }; 565 566 cpu@100010000 { 567 device_type = "cpu"; 568 compatible = "arm,cortex-a57"; 569 reg = <0x1 0x10000>; 570 enable-method = "spin-table"; 571 cpu-release-addr = <0 0x20000000>; 572 }; 573 574 cpu@100010001 { 575 device_type = "cpu"; 576 compatible = "arm,cortex-a57"; 577 reg = <0x1 0x10001>; 578 enable-method = "spin-table"; 579 cpu-release-addr = <0 0x20000000>; 580 }; 581 582 cpu@100010100 { 583 device_type = "cpu"; 584 compatible = "arm,cortex-a57"; 585 reg = <0x1 0x10100>; 586 enable-method = "spin-table"; 587 cpu-release-addr = <0 0x20000000>; 588 }; 589 590 cpu@100010101 { 591 device_type = "cpu"; 592 compatible = "arm,cortex-a57"; 593 reg = <0x1 0x10101>; 594 enable-method = "spin-table"; 595 cpu-release-addr = <0 0x20000000>; 596 }; 597 }; 598... 599