1# SPDX-License-Identifier: GPL-2.0 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/arm/cpus.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: ARM CPUs 8 9maintainers: 10 - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> 11 12description: |+ 13 The device tree allows to describe the layout of CPUs in a system through the 14 "cpus" node, which in turn contains a number of subnodes (ie "cpu") defining 15 properties for every cpu. 16 17 Bindings for CPU nodes follow the Devicetree Specification, available from: 18 19 https://www.devicetree.org/specifications/ 20 21 with updates for 32-bit and 64-bit ARM systems provided in this document. 22 23 ================================ 24 Convention used in this document 25 ================================ 26 27 This document follows the conventions described in the Devicetree 28 Specification, with the addition: 29 30 - square brackets define bitfields, eg reg[7:0] value of the bitfield in 31 the reg property contained in bits 7 down to 0 32 33 ===================================== 34 cpus and cpu node bindings definition 35 ===================================== 36 37 The ARM architecture, in accordance with the Devicetree Specification, 38 requires the cpus and cpu nodes to be present and contain the properties 39 described below. 40 41properties: 42 reg: 43 maxItems: 1 44 description: > 45 Usage and definition depend on ARM architecture version and configuration: 46 47 On uniprocessor ARM architectures previous to v7 this property is required 48 and must be set to 0. 49 50 On ARM 11 MPcore based systems this property is required and matches the 51 CPUID[11:0] register bits. 52 53 Bits [11:0] in the reg cell must be set to bits [11:0] in CPU ID register. 54 55 All other bits in the reg cell must be set to 0. 56 57 On 32-bit ARM v7 or later systems this property is required and matches 58 the CPU MPIDR[23:0] register bits. 59 60 Bits [23:0] in the reg cell must be set to bits [23:0] in MPIDR. 61 62 All other bits in the reg cell must be set to 0. 63 64 On ARM v8 64-bit systems this property is required and matches the 65 MPIDR_EL1 register affinity bits. 66 67 * If cpus node's #address-cells property is set to 2 68 69 The first reg cell bits [7:0] must be set to bits [39:32] of 70 MPIDR_EL1. 71 72 The second reg cell bits [23:0] must be set to bits [23:0] of 73 MPIDR_EL1. 74 75 * If cpus node's #address-cells property is set to 1 76 77 The reg cell bits [23:0] must be set to bits [23:0] of MPIDR_EL1. 78 79 All other bits in the reg cells must be set to 0. 80 81 compatible: 82 oneOf: 83 - enum: 84 - apm,potenza 85 - apm,strega 86 - apple,avalanche 87 - apple,blizzard 88 - apple,cyclone 89 - apple,everest 90 - apple,firestorm 91 - apple,hurricane-zephyr 92 - apple,icestorm 93 - apple,mistral 94 - apple,monsoon 95 - apple,sawtooth 96 - apple,twister 97 - apple,typhoon 98 - arm,arm710t 99 - arm,arm720t 100 - arm,arm740t 101 - arm,arm7ej-s 102 - arm,arm7tdmi 103 - arm,arm7tdmi-s 104 - arm,arm9es 105 - arm,arm9ej-s 106 - arm,arm920t 107 - arm,arm922t 108 - arm,arm925 109 - arm,arm926e-s 110 - arm,arm926ej-s 111 - arm,arm940t 112 - arm,arm946e-s 113 - arm,arm966e-s 114 - arm,arm968e-s 115 - arm,arm9tdmi 116 - arm,arm1020e 117 - arm,arm1020t 118 - arm,arm1022e 119 - arm,arm1026ej-s 120 - arm,arm1136j-s 121 - arm,arm1136jf-s 122 - arm,arm1156t2-s 123 - arm,arm1156t2f-s 124 - arm,arm1176jzf 125 - arm,arm1176jz-s 126 - arm,arm1176jzf-s 127 - arm,arm11mpcore 128 - arm,armv8 # Only for s/w models 129 - arm,c1-nano 130 - arm,c1-premium 131 - arm,c1-pro 132 - arm,c1-ultra 133 - arm,cortex-a5 134 - arm,cortex-a7 135 - arm,cortex-a8 136 - arm,cortex-a9 137 - arm,cortex-a12 138 - arm,cortex-a15 139 - arm,cortex-a17 140 - arm,cortex-a32 141 - arm,cortex-a34 142 - arm,cortex-a35 143 - arm,cortex-a53 144 - arm,cortex-a55 145 - arm,cortex-a57 146 - arm,cortex-a65 147 - arm,cortex-a72 148 - arm,cortex-a73 149 - arm,cortex-a75 150 - arm,cortex-a76 151 - arm,cortex-a77 152 - arm,cortex-a78 153 - arm,cortex-a78ae 154 - arm,cortex-a78c 155 - arm,cortex-a320 156 - arm,cortex-a510 157 - arm,cortex-a520 158 - arm,cortex-a520ae 159 - arm,cortex-a710 160 - arm,cortex-a715 161 - arm,cortex-a720 162 - arm,cortex-a720ae 163 - arm,cortex-a725 164 - arm,cortex-m0 165 - arm,cortex-m0+ 166 - arm,cortex-m1 167 - arm,cortex-m3 168 - arm,cortex-m4 169 - arm,cortex-r4 170 - arm,cortex-r5 171 - arm,cortex-r7 172 - arm,cortex-r52 173 - arm,cortex-x1 174 - arm,cortex-x1c 175 - arm,cortex-x2 176 - arm,cortex-x3 177 - arm,cortex-x4 178 - arm,cortex-x925 179 - arm,neoverse-e1 180 - arm,neoverse-n1 181 - arm,neoverse-n2 182 - arm,neoverse-n3 183 - arm,neoverse-v1 184 - arm,neoverse-v2 185 - arm,neoverse-v3 186 - arm,neoverse-v3ae 187 - arm,rainier 188 - brcm,brahma-b15 189 - brcm,brahma-b53 190 - brcm,vulcan 191 - cavium,thunder 192 - cavium,thunder2 193 - faraday,fa526 194 - intel,sa110 195 - intel,sa1100 196 - marvell,feroceon 197 - marvell,mohawk 198 - marvell,pj4a 199 - marvell,pj4b 200 - marvell,sheeva-v5 201 - marvell,sheeva-v7 202 - nvidia,tegra132-denver 203 - nvidia,tegra186-denver 204 - nvidia,tegra194-carmel 205 - qcom,krait 206 - qcom,kryo240 207 - qcom,kryo250 208 - qcom,kryo260 209 - qcom,kryo280 210 - qcom,kryo360 211 - qcom,kryo385 212 - qcom,kryo465 213 - qcom,kryo468 214 - qcom,kryo470 215 - qcom,kryo485 216 - qcom,kryo560 217 - qcom,kryo570 218 - qcom,kryo660 219 - qcom,kryo670 220 - qcom,kryo685 221 - qcom,kryo780 222 - qcom,scorpion 223 - samsung,mongoose-m2 224 - samsung,mongoose-m3 225 - samsung,mongoose-m5 226 - enum: 227 - qcom,kryo 228 - qcom,oryon 229 # Too generic, do not use in new code 230 deprecated: true 231 232 enable-method: 233 $ref: /schemas/types.yaml#/definitions/string 234 oneOf: 235 # On ARM v8 64-bit this property is required 236 - enum: 237 - psci 238 - spin-table 239 # On ARM 32-bit systems this property is optional 240 - enum: 241 - actions,s500-smp 242 - allwinner,sun6i-a31 243 - allwinner,sun8i-a23 244 - allwinner,sun9i-a80-smp 245 - allwinner,sun8i-a83t-smp 246 - amlogic,meson8-smp 247 - amlogic,meson8b-smp 248 - arm,realview-smp 249 - aspeed,ast2600-smp 250 - brcm,bcm11351-cpu-method 251 - brcm,bcm23550 252 - brcm,bcm2836-smp 253 - brcm,bcm63138 254 - brcm,bcm-nsp-smp 255 - brcm,brahma-b15 256 - marvell,armada-375-smp 257 - marvell,armada-380-smp 258 - marvell,armada-390-smp 259 - marvell,armada-xp-smp 260 - marvell,98dx3236-smp 261 - marvell,mmp3-smp 262 - mediatek,mt6589-smp 263 - mediatek,mt81xx-tz-smp 264 - qcom,gcc-msm8660 265 - qcom,kpss-acc-v1 266 - qcom,kpss-acc-v2 267 - qcom,msm8226-smp 268 - qcom,msm8909-smp 269 # Only valid on ARM 32-bit, see above for ARM v8 64-bit 270 - qcom,msm8916-smp 271 - renesas,apmu 272 - renesas,r9a06g032-smp 273 - rockchip,rk3036-smp 274 - rockchip,rk3066-smp 275 - socionext,milbeaut-m10v-smp 276 - ste,dbx500-smp 277 - ti,am3352 278 - ti,am4372 279 280 cpu-release-addr: 281 oneOf: 282 - $ref: /schemas/types.yaml#/definitions/uint32 283 - $ref: /schemas/types.yaml#/definitions/uint64 284 description: 285 The DT specification defines this as 64-bit always, but some 32-bit Arm 286 systems have used a 32-bit value which must be supported. 287 288 cpu-idle-states: 289 $ref: /schemas/types.yaml#/definitions/phandle-array 290 items: 291 maxItems: 1 292 description: 293 List of phandles to idle state nodes supported by this cpu (see 294 ./idle-states.yaml). 295 296 capacity-dmips-mhz: 297 description: 298 u32 value representing CPU capacity (see ../cpu/cpu-capacity.txt) in 299 DMIPS/MHz, relative to highest capacity-dmips-mhz in the system. 300 301 cci-control-port: true 302 303 dynamic-power-coefficient: 304 $ref: /schemas/types.yaml#/definitions/uint32 305 description: > 306 A u32 value that represents the running time dynamic power coefficient in 307 units of uW/MHz/V^2. The coefficient can either be calculated from power 308 measurements or derived by analysis. 309 310 The dynamic power consumption of the CPU is proportional to the square of 311 the Voltage (V) and the clock frequency (f). The coefficient is used to 312 calculate the dynamic power as below - 313 314 Pdyn = dynamic-power-coefficient * V^2 * f 315 316 where voltage is in V, frequency is in MHz. 317 318 interconnects: 319 minItems: 1 320 maxItems: 3 321 322 nvmem-cells: 323 maxItems: 1 324 325 nvmem-cell-names: 326 const: speed_grade 327 328 performance-domains: 329 maxItems: 1 330 331 power-domains: 332 minItems: 1 333 maxItems: 2 334 335 power-domain-names: 336 description: 337 For PSCI based platforms, the name corresponding to the index of the PSCI 338 PM domain provider, must be "psci". For SCMI based platforms, the name 339 corresponding to the index of an SCMI performance domain provider, must be 340 "perf". 341 minItems: 1 342 maxItems: 2 343 items: 344 enum: [ psci, perf, cpr ] 345 346 resets: 347 maxItems: 1 348 349 arm-supply: 350 deprecated: true 351 description: Use 'cpu-supply' instead 352 353 cpu0-supply: 354 deprecated: true 355 description: Use 'cpu-supply' instead 356 357 mem-supply: true 358 359 proc-supply: 360 deprecated: true 361 description: Use 'cpu-supply' instead 362 363 pu-supply: 364 deprecated: true 365 description: Only for i.MX6Q/DL/SL SoCs. 366 367 soc-supply: 368 deprecated: true 369 description: Only for i.MX6/7 Soc. 370 371 sram-supply: 372 deprecated: true 373 description: Use 'mem-supply' instead 374 375 fsl,soc-operating-points: 376 $ref: /schemas/types.yaml#/definitions/uint32-matrix 377 description: FSL i.MX6 Soc operation-points when change cpu frequency 378 deprecated: true 379 items: 380 items: 381 - description: Frequency in kHz 382 - description: Voltage for OPP in uV 383 384 mediatek,cci: 385 $ref: /schemas/types.yaml#/definitions/phandle 386 description: Link to Mediatek Cache Coherent Interconnect 387 388 edac-enabled: 389 $ref: /schemas/types.yaml#/definitions/flag 390 description: 391 A72 CPUs support Error Detection And Correction (EDAC) on their L1 and 392 L2 caches. This flag marks this function as usable. 393 394 qcom,saw: 395 $ref: /schemas/types.yaml#/definitions/phandle 396 description: 397 Specifies the SAW node associated with this CPU. 398 399 qcom,acc: 400 $ref: /schemas/types.yaml#/definitions/phandle 401 description: 402 Specifies the ACC node associated with this CPU. 403 404 qcom,freq-domain: 405 description: Specifies the QCom CPUFREQ HW associated with the CPU. 406 $ref: /schemas/types.yaml#/definitions/phandle-array 407 maxItems: 1 408 409 rockchip,pmu: 410 $ref: /schemas/types.yaml#/definitions/phandle 411 description: > 412 Specifies the syscon node controlling the cpu core power domains. 413 414 Optional for systems that have an "enable-method" property value of 415 "rockchip,rk3066-smp". While optional, it is the preferred way to get 416 access to the cpu-core power-domains. 417 418 secondary-boot-reg: 419 $ref: /schemas/types.yaml#/definitions/uint32 420 description: > 421 Required for systems that have an "enable-method" property value of 422 "brcm,bcm11351-cpu-method", "brcm,bcm23550" or "brcm,bcm-nsp-smp". 423 424 This includes the following SoCs: 425 BCM11130, BCM11140, BCM11351, BCM28145, BCM28155, BCM21664, BCM23550, 426 BCM58522, BCM58525, BCM58535, BCM58622, BCM58623, BCM58625, BCM88312 427 428 The secondary-boot-reg property is a u32 value that specifies the 429 physical address of the register used to request the ROM holding pen 430 code release a secondary CPU. The value written to the register is 431 formed by encoding the target CPU id into the low bits of the 432 physical start address it should jump to. 433 434 thermal-idle: 435 type: object 436 437allOf: 438 - $ref: /schemas/cpu.yaml# 439 - $ref: /schemas/opp/opp-v1.yaml# 440 - if: 441 not: 442 properties: 443 compatible: 444 contains: 445 const: arm,cortex-a72 446 then: 447 # Allow edac-enabled only for Cortex A72 448 properties: 449 edac-enabled: false 450 451 - if: 452 # If the enable-method property contains one of those values 453 properties: 454 enable-method: 455 contains: 456 enum: 457 - brcm,bcm11351-cpu-method 458 - brcm,bcm23550 459 - brcm,bcm-nsp-smp 460 # and if enable-method is present 461 required: 462 - enable-method 463 then: 464 required: 465 - secondary-boot-reg 466 - if: 467 properties: 468 enable-method: 469 enum: 470 - spin-table 471 - renesas,r9a06g032-smp 472 required: 473 - enable-method 474 then: 475 required: 476 - cpu-release-addr 477 - if: 478 properties: 479 enable-method: 480 enum: 481 - qcom,kpss-acc-v1 482 - qcom,kpss-acc-v2 483 - qcom,msm8226-smp 484 - qcom,msm8916-smp 485 required: 486 - enable-method 487 then: 488 required: 489 - qcom,acc 490 - qcom,saw 491 else: 492 if: 493 # 2 Qualcomm platforms bootloaders need qcom,acc and qcom,saw yet use 494 # "spin-table" or "psci" enable-methods. Disallowing the properties for 495 # all other CPUs is the best we can do as there's not any way to 496 # distinguish these Qualcomm platforms. 497 not: 498 properties: 499 compatible: 500 const: arm,cortex-a53 501 then: 502 properties: 503 qcom,acc: false 504 qcom,saw: false 505 506required: 507 - device_type 508 - reg 509 - compatible 510 511dependencies: 512 rockchip,pmu: [enable-method] 513 514unevaluatedProperties: false 515 516examples: 517 - | 518 cpus { 519 #size-cells = <0>; 520 #address-cells = <1>; 521 522 cpu@0 { 523 device_type = "cpu"; 524 compatible = "arm,cortex-a15"; 525 reg = <0x0>; 526 }; 527 528 cpu@1 { 529 device_type = "cpu"; 530 compatible = "arm,cortex-a15"; 531 reg = <0x1>; 532 }; 533 534 cpu@100 { 535 device_type = "cpu"; 536 compatible = "arm,cortex-a7"; 537 reg = <0x100>; 538 }; 539 540 cpu@101 { 541 device_type = "cpu"; 542 compatible = "arm,cortex-a7"; 543 reg = <0x101>; 544 }; 545 }; 546 547 - | 548 // Example 2 (Cortex-A8 uniprocessor 32-bit system): 549 cpus { 550 #size-cells = <0>; 551 #address-cells = <1>; 552 553 cpu@0 { 554 device_type = "cpu"; 555 compatible = "arm,cortex-a8"; 556 reg = <0x0>; 557 }; 558 }; 559 560 - | 561 // Example 3 (ARM 926EJ-S uniprocessor 32-bit system): 562 cpus { 563 #size-cells = <0>; 564 #address-cells = <1>; 565 566 cpu@0 { 567 device_type = "cpu"; 568 compatible = "arm,arm926ej-s"; 569 reg = <0x0>; 570 }; 571 }; 572 573 - | 574 // Example 4 (ARM Cortex-A57 64-bit system): 575 cpus { 576 #size-cells = <0>; 577 #address-cells = <2>; 578 579 cpu@0 { 580 device_type = "cpu"; 581 compatible = "arm,cortex-a57"; 582 reg = <0x0 0x0>; 583 enable-method = "spin-table"; 584 cpu-release-addr = <0 0x20000000>; 585 }; 586 587 cpu@1 { 588 device_type = "cpu"; 589 compatible = "arm,cortex-a57"; 590 reg = <0x0 0x1>; 591 enable-method = "spin-table"; 592 cpu-release-addr = <0 0x20000000>; 593 }; 594 595 cpu@100 { 596 device_type = "cpu"; 597 compatible = "arm,cortex-a57"; 598 reg = <0x0 0x100>; 599 enable-method = "spin-table"; 600 cpu-release-addr = <0 0x20000000>; 601 }; 602 603 cpu@101 { 604 device_type = "cpu"; 605 compatible = "arm,cortex-a57"; 606 reg = <0x0 0x101>; 607 enable-method = "spin-table"; 608 cpu-release-addr = <0 0x20000000>; 609 }; 610 611 cpu@10000 { 612 device_type = "cpu"; 613 compatible = "arm,cortex-a57"; 614 reg = <0x0 0x10000>; 615 enable-method = "spin-table"; 616 cpu-release-addr = <0 0x20000000>; 617 }; 618 619 cpu@10001 { 620 device_type = "cpu"; 621 compatible = "arm,cortex-a57"; 622 reg = <0x0 0x10001>; 623 enable-method = "spin-table"; 624 cpu-release-addr = <0 0x20000000>; 625 }; 626 627 cpu@10100 { 628 device_type = "cpu"; 629 compatible = "arm,cortex-a57"; 630 reg = <0x0 0x10100>; 631 enable-method = "spin-table"; 632 cpu-release-addr = <0 0x20000000>; 633 }; 634 635 cpu@10101 { 636 device_type = "cpu"; 637 compatible = "arm,cortex-a57"; 638 reg = <0x0 0x10101>; 639 enable-method = "spin-table"; 640 cpu-release-addr = <0 0x20000000>; 641 }; 642 643 cpu@100000000 { 644 device_type = "cpu"; 645 compatible = "arm,cortex-a57"; 646 reg = <0x1 0x0>; 647 enable-method = "spin-table"; 648 cpu-release-addr = <0 0x20000000>; 649 }; 650 651 cpu@100000001 { 652 device_type = "cpu"; 653 compatible = "arm,cortex-a57"; 654 reg = <0x1 0x1>; 655 enable-method = "spin-table"; 656 cpu-release-addr = <0 0x20000000>; 657 }; 658 659 cpu@100000100 { 660 device_type = "cpu"; 661 compatible = "arm,cortex-a57"; 662 reg = <0x1 0x100>; 663 enable-method = "spin-table"; 664 cpu-release-addr = <0 0x20000000>; 665 }; 666 667 cpu@100000101 { 668 device_type = "cpu"; 669 compatible = "arm,cortex-a57"; 670 reg = <0x1 0x101>; 671 enable-method = "spin-table"; 672 cpu-release-addr = <0 0x20000000>; 673 }; 674 675 cpu@100010000 { 676 device_type = "cpu"; 677 compatible = "arm,cortex-a57"; 678 reg = <0x1 0x10000>; 679 enable-method = "spin-table"; 680 cpu-release-addr = <0 0x20000000>; 681 }; 682 683 cpu@100010001 { 684 device_type = "cpu"; 685 compatible = "arm,cortex-a57"; 686 reg = <0x1 0x10001>; 687 enable-method = "spin-table"; 688 cpu-release-addr = <0 0x20000000>; 689 }; 690 691 cpu@100010100 { 692 device_type = "cpu"; 693 compatible = "arm,cortex-a57"; 694 reg = <0x1 0x10100>; 695 enable-method = "spin-table"; 696 cpu-release-addr = <0 0x20000000>; 697 }; 698 699 cpu@100010101 { 700 device_type = "cpu"; 701 compatible = "arm,cortex-a57"; 702 reg = <0x1 0x10101>; 703 enable-method = "spin-table"; 704 cpu-release-addr = <0 0x20000000>; 705 }; 706 }; 707... 708