1# SPDX-License-Identifier: GPL-2.0 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/arm/cpus.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: ARM CPUs 8 9maintainers: 10 - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> 11 12description: |+ 13 The device tree allows to describe the layout of CPUs in a system through the 14 "cpus" node, which in turn contains a number of subnodes (ie "cpu") defining 15 properties for every cpu. 16 17 Bindings for CPU nodes follow the Devicetree Specification, available from: 18 19 https://www.devicetree.org/specifications/ 20 21 with updates for 32-bit and 64-bit ARM systems provided in this document. 22 23 ================================ 24 Convention used in this document 25 ================================ 26 27 This document follows the conventions described in the Devicetree 28 Specification, with the addition: 29 30 - square brackets define bitfields, eg reg[7:0] value of the bitfield in 31 the reg property contained in bits 7 down to 0 32 33 ===================================== 34 cpus and cpu node bindings definition 35 ===================================== 36 37 The ARM architecture, in accordance with the Devicetree Specification, 38 requires the cpus and cpu nodes to be present and contain the properties 39 described below. 40 41properties: 42 reg: 43 maxItems: 1 44 description: > 45 Usage and definition depend on ARM architecture version and configuration: 46 47 On uniprocessor ARM architectures previous to v7 this property is required 48 and must be set to 0. 49 50 On ARM 11 MPcore based systems this property is required and matches the 51 CPUID[11:0] register bits. 52 53 Bits [11:0] in the reg cell must be set to bits [11:0] in CPU ID register. 54 55 All other bits in the reg cell must be set to 0. 56 57 On 32-bit ARM v7 or later systems this property is required and matches 58 the CPU MPIDR[23:0] register bits. 59 60 Bits [23:0] in the reg cell must be set to bits [23:0] in MPIDR. 61 62 All other bits in the reg cell must be set to 0. 63 64 On ARM v8 64-bit systems this property is required and matches the 65 MPIDR_EL1 register affinity bits. 66 67 * If cpus node's #address-cells property is set to 2 68 69 The first reg cell bits [7:0] must be set to bits [39:32] of 70 MPIDR_EL1. 71 72 The second reg cell bits [23:0] must be set to bits [23:0] of 73 MPIDR_EL1. 74 75 * If cpus node's #address-cells property is set to 1 76 77 The reg cell bits [23:0] must be set to bits [23:0] of MPIDR_EL1. 78 79 All other bits in the reg cells must be set to 0. 80 81 compatible: 82 enum: 83 - apm,potenza 84 - apm,strega 85 - apple,avalanche 86 - apple,blizzard 87 - apple,cyclone 88 - apple,firestorm 89 - apple,hurricane-zephyr 90 - apple,icestorm 91 - apple,mistral 92 - apple,monsoon 93 - apple,twister 94 - apple,typhoon 95 - arm,arm710t 96 - arm,arm720t 97 - arm,arm740t 98 - arm,arm7ej-s 99 - arm,arm7tdmi 100 - arm,arm7tdmi-s 101 - arm,arm9es 102 - arm,arm9ej-s 103 - arm,arm920t 104 - arm,arm922t 105 - arm,arm925 106 - arm,arm926e-s 107 - arm,arm926ej-s 108 - arm,arm940t 109 - arm,arm946e-s 110 - arm,arm966e-s 111 - arm,arm968e-s 112 - arm,arm9tdmi 113 - arm,arm1020e 114 - arm,arm1020t 115 - arm,arm1022e 116 - arm,arm1026ej-s 117 - arm,arm1136j-s 118 - arm,arm1136jf-s 119 - arm,arm1156t2-s 120 - arm,arm1156t2f-s 121 - arm,arm1176jzf 122 - arm,arm1176jz-s 123 - arm,arm1176jzf-s 124 - arm,arm11mpcore 125 - arm,armv8 # Only for s/w models 126 - arm,c1-nano 127 - arm,c1-premium 128 - arm,c1-pro 129 - arm,c1-ultra 130 - arm,cortex-a5 131 - arm,cortex-a7 132 - arm,cortex-a8 133 - arm,cortex-a9 134 - arm,cortex-a12 135 - arm,cortex-a15 136 - arm,cortex-a17 137 - arm,cortex-a32 138 - arm,cortex-a34 139 - arm,cortex-a35 140 - arm,cortex-a53 141 - arm,cortex-a55 142 - arm,cortex-a57 143 - arm,cortex-a65 144 - arm,cortex-a72 145 - arm,cortex-a73 146 - arm,cortex-a75 147 - arm,cortex-a76 148 - arm,cortex-a77 149 - arm,cortex-a78 150 - arm,cortex-a78ae 151 - arm,cortex-a78c 152 - arm,cortex-a320 153 - arm,cortex-a510 154 - arm,cortex-a520 155 - arm,cortex-a520ae 156 - arm,cortex-a710 157 - arm,cortex-a715 158 - arm,cortex-a720 159 - arm,cortex-a720ae 160 - arm,cortex-a725 161 - arm,cortex-m0 162 - arm,cortex-m0+ 163 - arm,cortex-m1 164 - arm,cortex-m3 165 - arm,cortex-m4 166 - arm,cortex-r4 167 - arm,cortex-r5 168 - arm,cortex-r7 169 - arm,cortex-r52 170 - arm,cortex-x1 171 - arm,cortex-x1c 172 - arm,cortex-x2 173 - arm,cortex-x3 174 - arm,cortex-x4 175 - arm,cortex-x925 176 - arm,neoverse-e1 177 - arm,neoverse-n1 178 - arm,neoverse-n2 179 - arm,neoverse-n3 180 - arm,neoverse-v1 181 - arm,neoverse-v2 182 - arm,neoverse-v3 183 - arm,neoverse-v3ae 184 - arm,rainier 185 - brcm,brahma-b15 186 - brcm,brahma-b53 187 - brcm,vulcan 188 - cavium,thunder 189 - cavium,thunder2 190 - faraday,fa526 191 - intel,sa110 192 - intel,sa1100 193 - marvell,feroceon 194 - marvell,mohawk 195 - marvell,pj4a 196 - marvell,pj4b 197 - marvell,sheeva-v5 198 - marvell,sheeva-v7 199 - nvidia,tegra132-denver 200 - nvidia,tegra186-denver 201 - nvidia,tegra194-carmel 202 - qcom,krait 203 - qcom,kryo 204 - qcom,kryo240 205 - qcom,kryo250 206 - qcom,kryo260 207 - qcom,kryo280 208 - qcom,kryo360 209 - qcom,kryo385 210 - qcom,kryo465 211 - qcom,kryo468 212 - qcom,kryo470 213 - qcom,kryo485 214 - qcom,kryo560 215 - qcom,kryo570 216 - qcom,kryo660 217 - qcom,kryo670 218 - qcom,kryo685 219 - qcom,kryo780 220 - qcom,oryon 221 - qcom,scorpion 222 - samsung,mongoose-m2 223 - samsung,mongoose-m3 224 - samsung,mongoose-m5 225 226 enable-method: 227 $ref: /schemas/types.yaml#/definitions/string 228 oneOf: 229 # On ARM v8 64-bit this property is required 230 - enum: 231 - psci 232 - spin-table 233 # On ARM 32-bit systems this property is optional 234 - enum: 235 - actions,s500-smp 236 - allwinner,sun6i-a31 237 - allwinner,sun8i-a23 238 - allwinner,sun9i-a80-smp 239 - allwinner,sun8i-a83t-smp 240 - amlogic,meson8-smp 241 - amlogic,meson8b-smp 242 - arm,realview-smp 243 - aspeed,ast2600-smp 244 - brcm,bcm11351-cpu-method 245 - brcm,bcm23550 246 - brcm,bcm2836-smp 247 - brcm,bcm63138 248 - brcm,bcm-nsp-smp 249 - brcm,brahma-b15 250 - marvell,armada-375-smp 251 - marvell,armada-380-smp 252 - marvell,armada-390-smp 253 - marvell,armada-xp-smp 254 - marvell,98dx3236-smp 255 - marvell,mmp3-smp 256 - mediatek,mt6589-smp 257 - mediatek,mt81xx-tz-smp 258 - qcom,gcc-msm8660 259 - qcom,kpss-acc-v1 260 - qcom,kpss-acc-v2 261 - qcom,msm8226-smp 262 - qcom,msm8909-smp 263 # Only valid on ARM 32-bit, see above for ARM v8 64-bit 264 - qcom,msm8916-smp 265 - renesas,apmu 266 - renesas,r9a06g032-smp 267 - rockchip,rk3036-smp 268 - rockchip,rk3066-smp 269 - socionext,milbeaut-m10v-smp 270 - ste,dbx500-smp 271 - ti,am3352 272 - ti,am4372 273 274 cpu-release-addr: 275 oneOf: 276 - $ref: /schemas/types.yaml#/definitions/uint32 277 - $ref: /schemas/types.yaml#/definitions/uint64 278 description: 279 The DT specification defines this as 64-bit always, but some 32-bit Arm 280 systems have used a 32-bit value which must be supported. 281 282 cpu-idle-states: 283 $ref: /schemas/types.yaml#/definitions/phandle-array 284 items: 285 maxItems: 1 286 description: 287 List of phandles to idle state nodes supported by this cpu (see 288 ./idle-states.yaml). 289 290 capacity-dmips-mhz: 291 description: 292 u32 value representing CPU capacity (see ../cpu/cpu-capacity.txt) in 293 DMIPS/MHz, relative to highest capacity-dmips-mhz in the system. 294 295 cci-control-port: true 296 297 dynamic-power-coefficient: 298 $ref: /schemas/types.yaml#/definitions/uint32 299 description: > 300 A u32 value that represents the running time dynamic power coefficient in 301 units of uW/MHz/V^2. The coefficient can either be calculated from power 302 measurements or derived by analysis. 303 304 The dynamic power consumption of the CPU is proportional to the square of 305 the Voltage (V) and the clock frequency (f). The coefficient is used to 306 calculate the dynamic power as below - 307 308 Pdyn = dynamic-power-coefficient * V^2 * f 309 310 where voltage is in V, frequency is in MHz. 311 312 interconnects: 313 minItems: 1 314 maxItems: 3 315 316 nvmem-cells: 317 maxItems: 1 318 319 nvmem-cell-names: 320 const: speed_grade 321 322 performance-domains: 323 maxItems: 1 324 325 power-domains: 326 minItems: 1 327 maxItems: 2 328 329 power-domain-names: 330 description: 331 For PSCI based platforms, the name corresponding to the index of the PSCI 332 PM domain provider, must be "psci". For SCMI based platforms, the name 333 corresponding to the index of an SCMI performance domain provider, must be 334 "perf". 335 minItems: 1 336 maxItems: 2 337 items: 338 enum: [ psci, perf, cpr ] 339 340 resets: 341 maxItems: 1 342 343 arm-supply: 344 deprecated: true 345 description: Use 'cpu-supply' instead 346 347 cpu0-supply: 348 deprecated: true 349 description: Use 'cpu-supply' instead 350 351 mem-supply: true 352 353 proc-supply: 354 deprecated: true 355 description: Use 'cpu-supply' instead 356 357 pu-supply: 358 deprecated: true 359 description: Only for i.MX6Q/DL/SL SoCs. 360 361 soc-supply: 362 deprecated: true 363 description: Only for i.MX6/7 Soc. 364 365 sram-supply: 366 deprecated: true 367 description: Use 'mem-supply' instead 368 369 fsl,soc-operating-points: 370 $ref: /schemas/types.yaml#/definitions/uint32-matrix 371 description: FSL i.MX6 Soc operation-points when change cpu frequency 372 deprecated: true 373 items: 374 items: 375 - description: Frequency in kHz 376 - description: Voltage for OPP in uV 377 378 mediatek,cci: 379 $ref: /schemas/types.yaml#/definitions/phandle 380 description: Link to Mediatek Cache Coherent Interconnect 381 382 edac-enabled: 383 $ref: /schemas/types.yaml#/definitions/flag 384 description: 385 A72 CPUs support Error Detection And Correction (EDAC) on their L1 and 386 L2 caches. This flag marks this function as usable. 387 388 qcom,saw: 389 $ref: /schemas/types.yaml#/definitions/phandle 390 description: 391 Specifies the SAW node associated with this CPU. 392 393 qcom,acc: 394 $ref: /schemas/types.yaml#/definitions/phandle 395 description: 396 Specifies the ACC node associated with this CPU. 397 398 qcom,freq-domain: 399 description: Specifies the QCom CPUFREQ HW associated with the CPU. 400 $ref: /schemas/types.yaml#/definitions/phandle-array 401 maxItems: 1 402 403 rockchip,pmu: 404 $ref: /schemas/types.yaml#/definitions/phandle 405 description: > 406 Specifies the syscon node controlling the cpu core power domains. 407 408 Optional for systems that have an "enable-method" property value of 409 "rockchip,rk3066-smp". While optional, it is the preferred way to get 410 access to the cpu-core power-domains. 411 412 secondary-boot-reg: 413 $ref: /schemas/types.yaml#/definitions/uint32 414 description: > 415 Required for systems that have an "enable-method" property value of 416 "brcm,bcm11351-cpu-method", "brcm,bcm23550" or "brcm,bcm-nsp-smp". 417 418 This includes the following SoCs: 419 BCM11130, BCM11140, BCM11351, BCM28145, BCM28155, BCM21664, BCM23550, 420 BCM58522, BCM58525, BCM58535, BCM58622, BCM58623, BCM58625, BCM88312 421 422 The secondary-boot-reg property is a u32 value that specifies the 423 physical address of the register used to request the ROM holding pen 424 code release a secondary CPU. The value written to the register is 425 formed by encoding the target CPU id into the low bits of the 426 physical start address it should jump to. 427 428 thermal-idle: 429 type: object 430 431allOf: 432 - $ref: /schemas/cpu.yaml# 433 - $ref: /schemas/opp/opp-v1.yaml# 434 - if: 435 not: 436 properties: 437 compatible: 438 contains: 439 const: arm,cortex-a72 440 then: 441 # Allow edac-enabled only for Cortex A72 442 properties: 443 edac-enabled: false 444 445 - if: 446 # If the enable-method property contains one of those values 447 properties: 448 enable-method: 449 contains: 450 enum: 451 - brcm,bcm11351-cpu-method 452 - brcm,bcm23550 453 - brcm,bcm-nsp-smp 454 # and if enable-method is present 455 required: 456 - enable-method 457 then: 458 required: 459 - secondary-boot-reg 460 - if: 461 properties: 462 enable-method: 463 enum: 464 - spin-table 465 - renesas,r9a06g032-smp 466 required: 467 - enable-method 468 then: 469 required: 470 - cpu-release-addr 471 - if: 472 properties: 473 enable-method: 474 enum: 475 - qcom,kpss-acc-v1 476 - qcom,kpss-acc-v2 477 - qcom,msm8226-smp 478 - qcom,msm8916-smp 479 required: 480 - enable-method 481 then: 482 required: 483 - qcom,acc 484 - qcom,saw 485 else: 486 if: 487 # 2 Qualcomm platforms bootloaders need qcom,acc and qcom,saw yet use 488 # "spin-table" or "psci" enable-methods. Disallowing the properties for 489 # all other CPUs is the best we can do as there's not any way to 490 # distinguish these Qualcomm platforms. 491 not: 492 properties: 493 compatible: 494 const: arm,cortex-a53 495 then: 496 properties: 497 qcom,acc: false 498 qcom,saw: false 499 500required: 501 - device_type 502 - reg 503 - compatible 504 505dependencies: 506 rockchip,pmu: [enable-method] 507 508unevaluatedProperties: false 509 510examples: 511 - | 512 cpus { 513 #size-cells = <0>; 514 #address-cells = <1>; 515 516 cpu@0 { 517 device_type = "cpu"; 518 compatible = "arm,cortex-a15"; 519 reg = <0x0>; 520 }; 521 522 cpu@1 { 523 device_type = "cpu"; 524 compatible = "arm,cortex-a15"; 525 reg = <0x1>; 526 }; 527 528 cpu@100 { 529 device_type = "cpu"; 530 compatible = "arm,cortex-a7"; 531 reg = <0x100>; 532 }; 533 534 cpu@101 { 535 device_type = "cpu"; 536 compatible = "arm,cortex-a7"; 537 reg = <0x101>; 538 }; 539 }; 540 541 - | 542 // Example 2 (Cortex-A8 uniprocessor 32-bit system): 543 cpus { 544 #size-cells = <0>; 545 #address-cells = <1>; 546 547 cpu@0 { 548 device_type = "cpu"; 549 compatible = "arm,cortex-a8"; 550 reg = <0x0>; 551 }; 552 }; 553 554 - | 555 // Example 3 (ARM 926EJ-S uniprocessor 32-bit system): 556 cpus { 557 #size-cells = <0>; 558 #address-cells = <1>; 559 560 cpu@0 { 561 device_type = "cpu"; 562 compatible = "arm,arm926ej-s"; 563 reg = <0x0>; 564 }; 565 }; 566 567 - | 568 // Example 4 (ARM Cortex-A57 64-bit system): 569 cpus { 570 #size-cells = <0>; 571 #address-cells = <2>; 572 573 cpu@0 { 574 device_type = "cpu"; 575 compatible = "arm,cortex-a57"; 576 reg = <0x0 0x0>; 577 enable-method = "spin-table"; 578 cpu-release-addr = <0 0x20000000>; 579 }; 580 581 cpu@1 { 582 device_type = "cpu"; 583 compatible = "arm,cortex-a57"; 584 reg = <0x0 0x1>; 585 enable-method = "spin-table"; 586 cpu-release-addr = <0 0x20000000>; 587 }; 588 589 cpu@100 { 590 device_type = "cpu"; 591 compatible = "arm,cortex-a57"; 592 reg = <0x0 0x100>; 593 enable-method = "spin-table"; 594 cpu-release-addr = <0 0x20000000>; 595 }; 596 597 cpu@101 { 598 device_type = "cpu"; 599 compatible = "arm,cortex-a57"; 600 reg = <0x0 0x101>; 601 enable-method = "spin-table"; 602 cpu-release-addr = <0 0x20000000>; 603 }; 604 605 cpu@10000 { 606 device_type = "cpu"; 607 compatible = "arm,cortex-a57"; 608 reg = <0x0 0x10000>; 609 enable-method = "spin-table"; 610 cpu-release-addr = <0 0x20000000>; 611 }; 612 613 cpu@10001 { 614 device_type = "cpu"; 615 compatible = "arm,cortex-a57"; 616 reg = <0x0 0x10001>; 617 enable-method = "spin-table"; 618 cpu-release-addr = <0 0x20000000>; 619 }; 620 621 cpu@10100 { 622 device_type = "cpu"; 623 compatible = "arm,cortex-a57"; 624 reg = <0x0 0x10100>; 625 enable-method = "spin-table"; 626 cpu-release-addr = <0 0x20000000>; 627 }; 628 629 cpu@10101 { 630 device_type = "cpu"; 631 compatible = "arm,cortex-a57"; 632 reg = <0x0 0x10101>; 633 enable-method = "spin-table"; 634 cpu-release-addr = <0 0x20000000>; 635 }; 636 637 cpu@100000000 { 638 device_type = "cpu"; 639 compatible = "arm,cortex-a57"; 640 reg = <0x1 0x0>; 641 enable-method = "spin-table"; 642 cpu-release-addr = <0 0x20000000>; 643 }; 644 645 cpu@100000001 { 646 device_type = "cpu"; 647 compatible = "arm,cortex-a57"; 648 reg = <0x1 0x1>; 649 enable-method = "spin-table"; 650 cpu-release-addr = <0 0x20000000>; 651 }; 652 653 cpu@100000100 { 654 device_type = "cpu"; 655 compatible = "arm,cortex-a57"; 656 reg = <0x1 0x100>; 657 enable-method = "spin-table"; 658 cpu-release-addr = <0 0x20000000>; 659 }; 660 661 cpu@100000101 { 662 device_type = "cpu"; 663 compatible = "arm,cortex-a57"; 664 reg = <0x1 0x101>; 665 enable-method = "spin-table"; 666 cpu-release-addr = <0 0x20000000>; 667 }; 668 669 cpu@100010000 { 670 device_type = "cpu"; 671 compatible = "arm,cortex-a57"; 672 reg = <0x1 0x10000>; 673 enable-method = "spin-table"; 674 cpu-release-addr = <0 0x20000000>; 675 }; 676 677 cpu@100010001 { 678 device_type = "cpu"; 679 compatible = "arm,cortex-a57"; 680 reg = <0x1 0x10001>; 681 enable-method = "spin-table"; 682 cpu-release-addr = <0 0x20000000>; 683 }; 684 685 cpu@100010100 { 686 device_type = "cpu"; 687 compatible = "arm,cortex-a57"; 688 reg = <0x1 0x10100>; 689 enable-method = "spin-table"; 690 cpu-release-addr = <0 0x20000000>; 691 }; 692 693 cpu@100010101 { 694 device_type = "cpu"; 695 compatible = "arm,cortex-a57"; 696 reg = <0x1 0x10101>; 697 enable-method = "spin-table"; 698 cpu-release-addr = <0 0x20000000>; 699 }; 700 }; 701... 702