1# SPDX-License-Identifier: GPL-2.0 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/arm/cpus.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: ARM CPUs 8 9maintainers: 10 - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> 11 12description: |+ 13 The device tree allows to describe the layout of CPUs in a system through the 14 "cpus" node, which in turn contains a number of subnodes (ie "cpu") defining 15 properties for every cpu. 16 17 Bindings for CPU nodes follow the Devicetree Specification, available from: 18 19 https://www.devicetree.org/specifications/ 20 21 with updates for 32-bit and 64-bit ARM systems provided in this document. 22 23 ================================ 24 Convention used in this document 25 ================================ 26 27 This document follows the conventions described in the Devicetree 28 Specification, with the addition: 29 30 - square brackets define bitfields, eg reg[7:0] value of the bitfield in 31 the reg property contained in bits 7 down to 0 32 33 ===================================== 34 cpus and cpu node bindings definition 35 ===================================== 36 37 The ARM architecture, in accordance with the Devicetree Specification, 38 requires the cpus and cpu nodes to be present and contain the properties 39 described below. 40 41properties: 42 reg: 43 maxItems: 1 44 description: > 45 Usage and definition depend on ARM architecture version and configuration: 46 47 On uniprocessor ARM architectures previous to v7 this property is required 48 and must be set to 0. 49 50 On ARM 11 MPcore based systems this property is required and matches the 51 CPUID[11:0] register bits. 52 53 Bits [11:0] in the reg cell must be set to bits [11:0] in CPU ID register. 54 55 All other bits in the reg cell must be set to 0. 56 57 On 32-bit ARM v7 or later systems this property is required and matches 58 the CPU MPIDR[23:0] register bits. 59 60 Bits [23:0] in the reg cell must be set to bits [23:0] in MPIDR. 61 62 All other bits in the reg cell must be set to 0. 63 64 On ARM v8 64-bit systems this property is required and matches the 65 MPIDR_EL1 register affinity bits. 66 67 * If cpus node's #address-cells property is set to 2 68 69 The first reg cell bits [7:0] must be set to bits [39:32] of 70 MPIDR_EL1. 71 72 The second reg cell bits [23:0] must be set to bits [23:0] of 73 MPIDR_EL1. 74 75 * If cpus node's #address-cells property is set to 1 76 77 The reg cell bits [23:0] must be set to bits [23:0] of MPIDR_EL1. 78 79 All other bits in the reg cells must be set to 0. 80 81 compatible: 82 oneOf: 83 - enum: 84 - apm,potenza 85 - apm,strega 86 - apple,avalanche 87 - apple,blizzard 88 - apple,cyclone 89 - apple,everest 90 - apple,firestorm 91 - apple,hurricane-zephyr 92 - apple,icestorm 93 - apple,mistral 94 - apple,monsoon 95 - apple,sawtooth 96 - apple,twister 97 - apple,typhoon 98 - arm,arm710t 99 - arm,arm720t 100 - arm,arm740t 101 - arm,arm7ej-s 102 - arm,arm7tdmi 103 - arm,arm7tdmi-s 104 - arm,arm9es 105 - arm,arm9ej-s 106 - arm,arm920t 107 - arm,arm922t 108 - arm,arm925 109 - arm,arm926e-s 110 - arm,arm926ej-s 111 - arm,arm940t 112 - arm,arm946e-s 113 - arm,arm966e-s 114 - arm,arm968e-s 115 - arm,arm9tdmi 116 - arm,arm1020e 117 - arm,arm1020t 118 - arm,arm1022e 119 - arm,arm1026ej-s 120 - arm,arm1136j-s 121 - arm,arm1136jf-s 122 - arm,arm1156t2-s 123 - arm,arm1156t2f-s 124 - arm,arm1176jzf 125 - arm,arm1176jz-s 126 - arm,arm1176jzf-s 127 - arm,arm11mpcore 128 - arm,armv8 # Only for s/w models 129 - arm,c1-nano 130 - arm,c1-premium 131 - arm,c1-pro 132 - arm,c1-ultra 133 - arm,cortex-a5 134 - arm,cortex-a7 135 - arm,cortex-a8 136 - arm,cortex-a9 137 - arm,cortex-a12 138 - arm,cortex-a15 139 - arm,cortex-a17 140 - arm,cortex-a32 141 - arm,cortex-a34 142 - arm,cortex-a35 143 - arm,cortex-a53 144 - arm,cortex-a55 145 - arm,cortex-a57 146 - arm,cortex-a65 147 - arm,cortex-a72 148 - arm,cortex-a73 149 - arm,cortex-a75 150 - arm,cortex-a76 151 - arm,cortex-a77 152 - arm,cortex-a78 153 - arm,cortex-a78ae 154 - arm,cortex-a78c 155 - arm,cortex-a320 156 - arm,cortex-a510 157 - arm,cortex-a520 158 - arm,cortex-a520ae 159 - arm,cortex-a710 160 - arm,cortex-a715 161 - arm,cortex-a720 162 - arm,cortex-a720ae 163 - arm,cortex-a725 164 - arm,cortex-m0 165 - arm,cortex-m0+ 166 - arm,cortex-m1 167 - arm,cortex-m3 168 - arm,cortex-m4 169 - arm,cortex-r4 170 - arm,cortex-r5 171 - arm,cortex-r7 172 - arm,cortex-r52 173 - arm,cortex-x1 174 - arm,cortex-x1c 175 - arm,cortex-x2 176 - arm,cortex-x3 177 - arm,cortex-x4 178 - arm,cortex-x925 179 - arm,neoverse-e1 180 - arm,neoverse-n1 181 - arm,neoverse-n2 182 - arm,neoverse-n3 183 - arm,neoverse-v1 184 - arm,neoverse-v2 185 - arm,neoverse-v3 186 - arm,neoverse-v3ae 187 - arm,rainier 188 - brcm,brahma-b15 189 - brcm,brahma-b53 190 - brcm,vulcan 191 - cavium,thunder 192 - cavium,thunder2 193 - faraday,fa526 194 - intel,sa110 195 - intel,sa1100 196 - marvell,feroceon 197 - marvell,mohawk 198 - marvell,pj4a 199 - marvell,pj4b 200 - marvell,sheeva-v5 201 - marvell,sheeva-v7 202 - nvidia,tegra132-denver 203 - nvidia,tegra186-denver 204 - nvidia,tegra194-carmel 205 - qcom,krait 206 - qcom,kryo240 207 - qcom,kryo250 208 - qcom,kryo260 209 - qcom,kryo280 210 - qcom,kryo360 211 - qcom,kryo385 212 - qcom,kryo465 213 - qcom,kryo468 214 - qcom,kryo470 215 - qcom,kryo485 216 - qcom,kryo560 217 - qcom,kryo570 218 - qcom,kryo660 219 - qcom,kryo670 220 - qcom,kryo685 221 - qcom,kryo780 222 - qcom,oryon-1-1 223 - qcom,oryon-1-2 224 - qcom,oryon-1-3 225 - qcom,oryon-1-4 226 - qcom,oryon-2-1 227 - qcom,oryon-2-2 228 - qcom,oryon-2-3 229 - qcom,scorpion 230 - samsung,mongoose-m2 231 - samsung,mongoose-m3 232 - samsung,mongoose-m5 233 - enum: 234 - qcom,kryo 235 - qcom,oryon 236 # Too generic, do not use in new code 237 deprecated: true 238 239 enable-method: 240 $ref: /schemas/types.yaml#/definitions/string 241 oneOf: 242 # On ARM v8 64-bit this property is required 243 - enum: 244 - psci 245 - spin-table 246 # On ARM 32-bit systems this property is optional 247 - enum: 248 - actions,s500-smp 249 - allwinner,sun6i-a31 250 - allwinner,sun8i-a23 251 - allwinner,sun9i-a80-smp 252 - allwinner,sun8i-a83t-smp 253 - amlogic,meson8-smp 254 - amlogic,meson8b-smp 255 - arm,realview-smp 256 - aspeed,ast2600-smp 257 - brcm,bcm11351-cpu-method 258 - brcm,bcm23550 259 - brcm,bcm2836-smp 260 - brcm,bcm63138 261 - brcm,bcm-nsp-smp 262 - brcm,brahma-b15 263 - marvell,armada-375-smp 264 - marvell,armada-380-smp 265 - marvell,armada-390-smp 266 - marvell,armada-xp-smp 267 - marvell,98dx3236-smp 268 - marvell,mmp3-smp 269 - mediatek,mt6589-smp 270 - mediatek,mt81xx-tz-smp 271 - qcom,gcc-msm8660 272 - qcom,kpss-acc-v1 273 - qcom,kpss-acc-v2 274 - qcom,msm8226-smp 275 - qcom,msm8909-smp 276 # Only valid on ARM 32-bit, see above for ARM v8 64-bit 277 - qcom,msm8916-smp 278 - renesas,apmu 279 - renesas,r9a06g032-smp 280 - rockchip,rk3036-smp 281 - rockchip,rk3066-smp 282 - socionext,milbeaut-m10v-smp 283 - ste,dbx500-smp 284 - ti,am3352 285 - ti,am4372 286 287 cpu-release-addr: 288 oneOf: 289 - $ref: /schemas/types.yaml#/definitions/uint32 290 - $ref: /schemas/types.yaml#/definitions/uint64 291 description: 292 The DT specification defines this as 64-bit always, but some 32-bit Arm 293 systems have used a 32-bit value which must be supported. 294 295 cpu-idle-states: 296 $ref: /schemas/types.yaml#/definitions/phandle-array 297 items: 298 maxItems: 1 299 description: 300 List of phandles to idle state nodes supported by this cpu (see 301 ./idle-states.yaml). 302 303 capacity-dmips-mhz: 304 description: 305 u32 value representing CPU capacity (see ../cpu/cpu-capacity.txt) in 306 DMIPS/MHz, relative to highest capacity-dmips-mhz in the system. 307 308 cci-control-port: true 309 310 dynamic-power-coefficient: 311 $ref: /schemas/types.yaml#/definitions/uint32 312 description: > 313 A u32 value that represents the running time dynamic power coefficient in 314 units of uW/MHz/V^2. The coefficient can either be calculated from power 315 measurements or derived by analysis. 316 317 The dynamic power consumption of the CPU is proportional to the square of 318 the Voltage (V) and the clock frequency (f). The coefficient is used to 319 calculate the dynamic power as below - 320 321 Pdyn = dynamic-power-coefficient * V^2 * f 322 323 where voltage is in V, frequency is in MHz. 324 325 interconnects: 326 minItems: 1 327 maxItems: 3 328 329 nvmem-cells: 330 maxItems: 1 331 332 nvmem-cell-names: 333 const: speed_grade 334 335 performance-domains: 336 maxItems: 1 337 338 power-domains: 339 minItems: 1 340 maxItems: 2 341 342 power-domain-names: 343 description: 344 For PSCI based platforms, the name corresponding to the index of the PSCI 345 PM domain provider, must be "psci". For SCMI based platforms, the name 346 corresponding to the index of an SCMI performance domain provider, must be 347 "perf". 348 minItems: 1 349 maxItems: 2 350 items: 351 enum: [ psci, perf, cpr ] 352 353 resets: 354 maxItems: 1 355 356 arm-supply: 357 deprecated: true 358 description: Use 'cpu-supply' instead 359 360 cpu0-supply: 361 deprecated: true 362 description: Use 'cpu-supply' instead 363 364 mem-supply: true 365 366 proc-supply: 367 deprecated: true 368 description: Use 'cpu-supply' instead 369 370 pu-supply: 371 deprecated: true 372 description: Only for i.MX6Q/DL/SL SoCs. 373 374 soc-supply: 375 deprecated: true 376 description: Only for i.MX6/7 Soc. 377 378 sram-supply: 379 deprecated: true 380 description: Use 'mem-supply' instead 381 382 fsl,soc-operating-points: 383 $ref: /schemas/types.yaml#/definitions/uint32-matrix 384 description: FSL i.MX6 Soc operation-points when change cpu frequency 385 deprecated: true 386 items: 387 items: 388 - description: Frequency in kHz 389 - description: Voltage for OPP in uV 390 391 mediatek,cci: 392 $ref: /schemas/types.yaml#/definitions/phandle 393 description: Link to Mediatek Cache Coherent Interconnect 394 395 edac-enabled: 396 $ref: /schemas/types.yaml#/definitions/flag 397 description: 398 A72 CPUs support Error Detection And Correction (EDAC) on their L1 and 399 L2 caches. This flag marks this function as usable. 400 401 qcom,saw: 402 $ref: /schemas/types.yaml#/definitions/phandle 403 description: 404 Specifies the SAW node associated with this CPU. 405 406 qcom,acc: 407 $ref: /schemas/types.yaml#/definitions/phandle 408 description: 409 Specifies the ACC node associated with this CPU. 410 411 qcom,freq-domain: 412 description: Specifies the QCom CPUFREQ HW associated with the CPU. 413 $ref: /schemas/types.yaml#/definitions/phandle-array 414 maxItems: 1 415 416 rockchip,pmu: 417 $ref: /schemas/types.yaml#/definitions/phandle 418 description: > 419 Specifies the syscon node controlling the cpu core power domains. 420 421 Optional for systems that have an "enable-method" property value of 422 "rockchip,rk3066-smp". While optional, it is the preferred way to get 423 access to the cpu-core power-domains. 424 425 secondary-boot-reg: 426 $ref: /schemas/types.yaml#/definitions/uint32 427 description: > 428 Required for systems that have an "enable-method" property value of 429 "brcm,bcm11351-cpu-method", "brcm,bcm23550" or "brcm,bcm-nsp-smp". 430 431 This includes the following SoCs: 432 BCM11130, BCM11140, BCM11351, BCM28145, BCM28155, BCM21664, BCM23550, 433 BCM58522, BCM58525, BCM58535, BCM58622, BCM58623, BCM58625, BCM88312 434 435 The secondary-boot-reg property is a u32 value that specifies the 436 physical address of the register used to request the ROM holding pen 437 code release a secondary CPU. The value written to the register is 438 formed by encoding the target CPU id into the low bits of the 439 physical start address it should jump to. 440 441 thermal-idle: 442 type: object 443 444allOf: 445 - $ref: /schemas/cpu.yaml# 446 - $ref: /schemas/opp/opp-v1.yaml# 447 - if: 448 not: 449 properties: 450 compatible: 451 contains: 452 const: arm,cortex-a72 453 then: 454 # Allow edac-enabled only for Cortex A72 455 properties: 456 edac-enabled: false 457 458 - if: 459 # If the enable-method property contains one of those values 460 properties: 461 enable-method: 462 contains: 463 enum: 464 - brcm,bcm11351-cpu-method 465 - brcm,bcm23550 466 - brcm,bcm-nsp-smp 467 # and if enable-method is present 468 required: 469 - enable-method 470 then: 471 required: 472 - secondary-boot-reg 473 - if: 474 properties: 475 enable-method: 476 enum: 477 - spin-table 478 - renesas,r9a06g032-smp 479 required: 480 - enable-method 481 then: 482 required: 483 - cpu-release-addr 484 - if: 485 properties: 486 enable-method: 487 enum: 488 - qcom,kpss-acc-v1 489 - qcom,kpss-acc-v2 490 - qcom,msm8226-smp 491 - qcom,msm8916-smp 492 required: 493 - enable-method 494 then: 495 required: 496 - qcom,acc 497 - qcom,saw 498 else: 499 if: 500 # 2 Qualcomm platforms bootloaders need qcom,acc and qcom,saw yet use 501 # "spin-table" or "psci" enable-methods. Disallowing the properties for 502 # all other CPUs is the best we can do as there's not any way to 503 # distinguish these Qualcomm platforms. 504 not: 505 properties: 506 compatible: 507 const: arm,cortex-a53 508 then: 509 properties: 510 qcom,acc: false 511 qcom,saw: false 512 513required: 514 - device_type 515 - reg 516 - compatible 517 518dependencies: 519 rockchip,pmu: [enable-method] 520 521unevaluatedProperties: false 522 523examples: 524 - | 525 cpus { 526 #size-cells = <0>; 527 #address-cells = <1>; 528 529 cpu@0 { 530 device_type = "cpu"; 531 compatible = "arm,cortex-a15"; 532 reg = <0x0>; 533 }; 534 535 cpu@1 { 536 device_type = "cpu"; 537 compatible = "arm,cortex-a15"; 538 reg = <0x1>; 539 }; 540 541 cpu@100 { 542 device_type = "cpu"; 543 compatible = "arm,cortex-a7"; 544 reg = <0x100>; 545 }; 546 547 cpu@101 { 548 device_type = "cpu"; 549 compatible = "arm,cortex-a7"; 550 reg = <0x101>; 551 }; 552 }; 553 554 - | 555 // Example 2 (Cortex-A8 uniprocessor 32-bit system): 556 cpus { 557 #size-cells = <0>; 558 #address-cells = <1>; 559 560 cpu@0 { 561 device_type = "cpu"; 562 compatible = "arm,cortex-a8"; 563 reg = <0x0>; 564 }; 565 }; 566 567 - | 568 // Example 3 (ARM 926EJ-S uniprocessor 32-bit system): 569 cpus { 570 #size-cells = <0>; 571 #address-cells = <1>; 572 573 cpu@0 { 574 device_type = "cpu"; 575 compatible = "arm,arm926ej-s"; 576 reg = <0x0>; 577 }; 578 }; 579 580 - | 581 // Example 4 (ARM Cortex-A57 64-bit system): 582 cpus { 583 #size-cells = <0>; 584 #address-cells = <2>; 585 586 cpu@0 { 587 device_type = "cpu"; 588 compatible = "arm,cortex-a57"; 589 reg = <0x0 0x0>; 590 enable-method = "spin-table"; 591 cpu-release-addr = <0 0x20000000>; 592 }; 593 594 cpu@1 { 595 device_type = "cpu"; 596 compatible = "arm,cortex-a57"; 597 reg = <0x0 0x1>; 598 enable-method = "spin-table"; 599 cpu-release-addr = <0 0x20000000>; 600 }; 601 602 cpu@100 { 603 device_type = "cpu"; 604 compatible = "arm,cortex-a57"; 605 reg = <0x0 0x100>; 606 enable-method = "spin-table"; 607 cpu-release-addr = <0 0x20000000>; 608 }; 609 610 cpu@101 { 611 device_type = "cpu"; 612 compatible = "arm,cortex-a57"; 613 reg = <0x0 0x101>; 614 enable-method = "spin-table"; 615 cpu-release-addr = <0 0x20000000>; 616 }; 617 618 cpu@10000 { 619 device_type = "cpu"; 620 compatible = "arm,cortex-a57"; 621 reg = <0x0 0x10000>; 622 enable-method = "spin-table"; 623 cpu-release-addr = <0 0x20000000>; 624 }; 625 626 cpu@10001 { 627 device_type = "cpu"; 628 compatible = "arm,cortex-a57"; 629 reg = <0x0 0x10001>; 630 enable-method = "spin-table"; 631 cpu-release-addr = <0 0x20000000>; 632 }; 633 634 cpu@10100 { 635 device_type = "cpu"; 636 compatible = "arm,cortex-a57"; 637 reg = <0x0 0x10100>; 638 enable-method = "spin-table"; 639 cpu-release-addr = <0 0x20000000>; 640 }; 641 642 cpu@10101 { 643 device_type = "cpu"; 644 compatible = "arm,cortex-a57"; 645 reg = <0x0 0x10101>; 646 enable-method = "spin-table"; 647 cpu-release-addr = <0 0x20000000>; 648 }; 649 650 cpu@100000000 { 651 device_type = "cpu"; 652 compatible = "arm,cortex-a57"; 653 reg = <0x1 0x0>; 654 enable-method = "spin-table"; 655 cpu-release-addr = <0 0x20000000>; 656 }; 657 658 cpu@100000001 { 659 device_type = "cpu"; 660 compatible = "arm,cortex-a57"; 661 reg = <0x1 0x1>; 662 enable-method = "spin-table"; 663 cpu-release-addr = <0 0x20000000>; 664 }; 665 666 cpu@100000100 { 667 device_type = "cpu"; 668 compatible = "arm,cortex-a57"; 669 reg = <0x1 0x100>; 670 enable-method = "spin-table"; 671 cpu-release-addr = <0 0x20000000>; 672 }; 673 674 cpu@100000101 { 675 device_type = "cpu"; 676 compatible = "arm,cortex-a57"; 677 reg = <0x1 0x101>; 678 enable-method = "spin-table"; 679 cpu-release-addr = <0 0x20000000>; 680 }; 681 682 cpu@100010000 { 683 device_type = "cpu"; 684 compatible = "arm,cortex-a57"; 685 reg = <0x1 0x10000>; 686 enable-method = "spin-table"; 687 cpu-release-addr = <0 0x20000000>; 688 }; 689 690 cpu@100010001 { 691 device_type = "cpu"; 692 compatible = "arm,cortex-a57"; 693 reg = <0x1 0x10001>; 694 enable-method = "spin-table"; 695 cpu-release-addr = <0 0x20000000>; 696 }; 697 698 cpu@100010100 { 699 device_type = "cpu"; 700 compatible = "arm,cortex-a57"; 701 reg = <0x1 0x10100>; 702 enable-method = "spin-table"; 703 cpu-release-addr = <0 0x20000000>; 704 }; 705 706 cpu@100010101 { 707 device_type = "cpu"; 708 compatible = "arm,cortex-a57"; 709 reg = <0x1 0x10101>; 710 enable-method = "spin-table"; 711 cpu-release-addr = <0 0x20000000>; 712 }; 713 }; 714... 715