1# SPDX-License-Identifier: GPL-2.0 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/arm/cpus.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: ARM CPUs 8 9maintainers: 10 - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> 11 12description: |+ 13 The device tree allows to describe the layout of CPUs in a system through the 14 "cpus" node, which in turn contains a number of subnodes (ie "cpu") defining 15 properties for every cpu. 16 17 Bindings for CPU nodes follow the Devicetree Specification, available from: 18 19 https://www.devicetree.org/specifications/ 20 21 with updates for 32-bit and 64-bit ARM systems provided in this document. 22 23 ================================ 24 Convention used in this document 25 ================================ 26 27 This document follows the conventions described in the Devicetree 28 Specification, with the addition: 29 30 - square brackets define bitfields, eg reg[7:0] value of the bitfield in 31 the reg property contained in bits 7 down to 0 32 33 ===================================== 34 cpus and cpu node bindings definition 35 ===================================== 36 37 The ARM architecture, in accordance with the Devicetree Specification, 38 requires the cpus and cpu nodes to be present and contain the properties 39 described below. 40 41properties: 42 reg: 43 maxItems: 1 44 description: > 45 Usage and definition depend on ARM architecture version and configuration: 46 47 On uniprocessor ARM architectures previous to v7 this property is required 48 and must be set to 0. 49 50 On ARM 11 MPcore based systems this property is required and matches the 51 CPUID[11:0] register bits. 52 53 Bits [11:0] in the reg cell must be set to bits [11:0] in CPU ID register. 54 55 All other bits in the reg cell must be set to 0. 56 57 On 32-bit ARM v7 or later systems this property is required and matches 58 the CPU MPIDR[23:0] register bits. 59 60 Bits [23:0] in the reg cell must be set to bits [23:0] in MPIDR. 61 62 All other bits in the reg cell must be set to 0. 63 64 On ARM v8 64-bit systems this property is required and matches the 65 MPIDR_EL1 register affinity bits. 66 67 * If cpus node's #address-cells property is set to 2 68 69 The first reg cell bits [7:0] must be set to bits [39:32] of 70 MPIDR_EL1. 71 72 The second reg cell bits [23:0] must be set to bits [23:0] of 73 MPIDR_EL1. 74 75 * If cpus node's #address-cells property is set to 1 76 77 The reg cell bits [23:0] must be set to bits [23:0] of MPIDR_EL1. 78 79 All other bits in the reg cells must be set to 0. 80 81 compatible: 82 enum: 83 - apple,avalanche 84 - apple,blizzard 85 - apple,cyclone 86 - apple,firestorm 87 - apple,hurricane-zephyr 88 - apple,icestorm 89 - apple,mistral 90 - apple,monsoon 91 - apple,twister 92 - apple,typhoon 93 - arm,arm710t 94 - arm,arm720t 95 - arm,arm740t 96 - arm,arm7ej-s 97 - arm,arm7tdmi 98 - arm,arm7tdmi-s 99 - arm,arm9es 100 - arm,arm9ej-s 101 - arm,arm920t 102 - arm,arm922t 103 - arm,arm925 104 - arm,arm926e-s 105 - arm,arm926ej-s 106 - arm,arm940t 107 - arm,arm946e-s 108 - arm,arm966e-s 109 - arm,arm968e-s 110 - arm,arm9tdmi 111 - arm,arm1020e 112 - arm,arm1020t 113 - arm,arm1022e 114 - arm,arm1026ej-s 115 - arm,arm1136j-s 116 - arm,arm1136jf-s 117 - arm,arm1156t2-s 118 - arm,arm1156t2f-s 119 - arm,arm1176jzf 120 - arm,arm1176jz-s 121 - arm,arm1176jzf-s 122 - arm,arm11mpcore 123 - arm,armv8 # Only for s/w models 124 - arm,cortex-a5 125 - arm,cortex-a7 126 - arm,cortex-a8 127 - arm,cortex-a9 128 - arm,cortex-a12 129 - arm,cortex-a15 130 - arm,cortex-a17 131 - arm,cortex-a32 132 - arm,cortex-a34 133 - arm,cortex-a35 134 - arm,cortex-a53 135 - arm,cortex-a55 136 - arm,cortex-a57 137 - arm,cortex-a65 138 - arm,cortex-a72 139 - arm,cortex-a73 140 - arm,cortex-a75 141 - arm,cortex-a76 142 - arm,cortex-a77 143 - arm,cortex-a78 144 - arm,cortex-a78ae 145 - arm,cortex-a78c 146 - arm,cortex-a510 147 - arm,cortex-a520 148 - arm,cortex-a710 149 - arm,cortex-a715 150 - arm,cortex-a720 151 - arm,cortex-a725 152 - arm,cortex-m0 153 - arm,cortex-m0+ 154 - arm,cortex-m1 155 - arm,cortex-m3 156 - arm,cortex-m4 157 - arm,cortex-r4 158 - arm,cortex-r5 159 - arm,cortex-r7 160 - arm,cortex-r52 161 - arm,cortex-x1 162 - arm,cortex-x1c 163 - arm,cortex-x2 164 - arm,cortex-x3 165 - arm,cortex-x4 166 - arm,cortex-x925 167 - arm,neoverse-e1 168 - arm,neoverse-n1 169 - arm,neoverse-n2 170 - arm,neoverse-n3 171 - arm,neoverse-v1 172 - arm,neoverse-v2 173 - arm,neoverse-v3 174 - arm,neoverse-v3ae 175 - arm,rainier 176 - brcm,brahma-b15 177 - brcm,brahma-b53 178 - brcm,vulcan 179 - cavium,thunder 180 - cavium,thunder2 181 - faraday,fa526 182 - intel,sa110 183 - intel,sa1100 184 - marvell,feroceon 185 - marvell,mohawk 186 - marvell,pj4a 187 - marvell,pj4b 188 - marvell,sheeva-v5 189 - marvell,sheeva-v7 190 - nvidia,tegra132-denver 191 - nvidia,tegra186-denver 192 - nvidia,tegra194-carmel 193 - qcom,krait 194 - qcom,kryo 195 - qcom,kryo240 196 - qcom,kryo250 197 - qcom,kryo260 198 - qcom,kryo280 199 - qcom,kryo360 200 - qcom,kryo385 201 - qcom,kryo465 202 - qcom,kryo468 203 - qcom,kryo485 204 - qcom,kryo560 205 - qcom,kryo570 206 - qcom,kryo660 207 - qcom,kryo670 208 - qcom,kryo685 209 - qcom,kryo780 210 - qcom,oryon 211 - qcom,scorpion 212 - samsung,mongoose-m2 213 - samsung,mongoose-m3 214 - samsung,mongoose-m5 215 216 enable-method: 217 $ref: /schemas/types.yaml#/definitions/string 218 oneOf: 219 # On ARM v8 64-bit this property is required 220 - enum: 221 - psci 222 - spin-table 223 # On ARM 32-bit systems this property is optional 224 - enum: 225 - actions,s500-smp 226 - allwinner,sun6i-a31 227 - allwinner,sun8i-a23 228 - allwinner,sun9i-a80-smp 229 - allwinner,sun8i-a83t-smp 230 - amlogic,meson8-smp 231 - amlogic,meson8b-smp 232 - arm,realview-smp 233 - aspeed,ast2600-smp 234 - brcm,bcm11351-cpu-method 235 - brcm,bcm23550 236 - brcm,bcm2836-smp 237 - brcm,bcm63138 238 - brcm,bcm-nsp-smp 239 - brcm,brahma-b15 240 - marvell,armada-375-smp 241 - marvell,armada-380-smp 242 - marvell,armada-390-smp 243 - marvell,armada-xp-smp 244 - marvell,98dx3236-smp 245 - marvell,mmp3-smp 246 - mediatek,mt6589-smp 247 - mediatek,mt81xx-tz-smp 248 - qcom,gcc-msm8660 249 - qcom,kpss-acc-v1 250 - qcom,kpss-acc-v2 251 - qcom,msm8226-smp 252 - qcom,msm8909-smp 253 # Only valid on ARM 32-bit, see above for ARM v8 64-bit 254 - qcom,msm8916-smp 255 - renesas,apmu 256 - renesas,r9a06g032-smp 257 - rockchip,rk3036-smp 258 - rockchip,rk3066-smp 259 - socionext,milbeaut-m10v-smp 260 - ste,dbx500-smp 261 - ti,am3352 262 - ti,am4372 263 264 cpu-release-addr: 265 oneOf: 266 - $ref: /schemas/types.yaml#/definitions/uint32 267 - $ref: /schemas/types.yaml#/definitions/uint64 268 description: 269 The DT specification defines this as 64-bit always, but some 32-bit Arm 270 systems have used a 32-bit value which must be supported. 271 272 cpu-idle-states: 273 $ref: /schemas/types.yaml#/definitions/phandle-array 274 items: 275 maxItems: 1 276 description: 277 List of phandles to idle state nodes supported by this cpu (see 278 ./idle-states.yaml). 279 280 capacity-dmips-mhz: 281 description: 282 u32 value representing CPU capacity (see ../cpu/cpu-capacity.txt) in 283 DMIPS/MHz, relative to highest capacity-dmips-mhz in the system. 284 285 cci-control-port: true 286 287 dynamic-power-coefficient: 288 $ref: /schemas/types.yaml#/definitions/uint32 289 description: > 290 A u32 value that represents the running time dynamic power coefficient in 291 units of uW/MHz/V^2. The coefficient can either be calculated from power 292 measurements or derived by analysis. 293 294 The dynamic power consumption of the CPU is proportional to the square of 295 the Voltage (V) and the clock frequency (f). The coefficient is used to 296 calculate the dynamic power as below - 297 298 Pdyn = dynamic-power-coefficient * V^2 * f 299 300 where voltage is in V, frequency is in MHz. 301 302 interconnects: 303 minItems: 1 304 maxItems: 3 305 306 nvmem-cells: 307 maxItems: 1 308 309 nvmem-cell-names: 310 const: speed_grade 311 312 performance-domains: 313 maxItems: 1 314 315 power-domains: 316 minItems: 1 317 maxItems: 2 318 319 power-domain-names: 320 description: 321 For PSCI based platforms, the name corresponding to the index of the PSCI 322 PM domain provider, must be "psci". For SCMI based platforms, the name 323 corresponding to the index of an SCMI performance domain provider, must be 324 "perf". 325 minItems: 1 326 maxItems: 2 327 items: 328 enum: [ psci, perf, cpr ] 329 330 resets: 331 maxItems: 1 332 333 arm-supply: 334 deprecated: true 335 description: Use 'cpu-supply' instead 336 337 cpu0-supply: 338 deprecated: true 339 description: Use 'cpu-supply' instead 340 341 mem-supply: true 342 343 proc-supply: 344 deprecated: true 345 description: Use 'cpu-supply' instead 346 347 sram-supply: 348 deprecated: true 349 description: Use 'mem-supply' instead 350 351 mediatek,cci: 352 $ref: /schemas/types.yaml#/definitions/phandle 353 description: Link to Mediatek Cache Coherent Interconnect 354 355 qcom,saw: 356 $ref: /schemas/types.yaml#/definitions/phandle 357 description: 358 Specifies the SAW node associated with this CPU. 359 360 qcom,acc: 361 $ref: /schemas/types.yaml#/definitions/phandle 362 description: 363 Specifies the ACC node associated with this CPU. 364 365 qcom,freq-domain: 366 description: Specifies the QCom CPUFREQ HW associated with the CPU. 367 $ref: /schemas/types.yaml#/definitions/phandle-array 368 maxItems: 1 369 370 rockchip,pmu: 371 $ref: /schemas/types.yaml#/definitions/phandle 372 description: > 373 Specifies the syscon node controlling the cpu core power domains. 374 375 Optional for systems that have an "enable-method" property value of 376 "rockchip,rk3066-smp". While optional, it is the preferred way to get 377 access to the cpu-core power-domains. 378 379 secondary-boot-reg: 380 $ref: /schemas/types.yaml#/definitions/uint32 381 description: > 382 Required for systems that have an "enable-method" property value of 383 "brcm,bcm11351-cpu-method", "brcm,bcm23550" or "brcm,bcm-nsp-smp". 384 385 This includes the following SoCs: 386 BCM11130, BCM11140, BCM11351, BCM28145, BCM28155, BCM21664, BCM23550, 387 BCM58522, BCM58525, BCM58535, BCM58622, BCM58623, BCM58625, BCM88312 388 389 The secondary-boot-reg property is a u32 value that specifies the 390 physical address of the register used to request the ROM holding pen 391 code release a secondary CPU. The value written to the register is 392 formed by encoding the target CPU id into the low bits of the 393 physical start address it should jump to. 394 395 thermal-idle: 396 type: object 397 398allOf: 399 - $ref: /schemas/cpu.yaml# 400 - $ref: /schemas/opp/opp-v1.yaml# 401 - if: 402 # If the enable-method property contains one of those values 403 properties: 404 enable-method: 405 contains: 406 enum: 407 - brcm,bcm11351-cpu-method 408 - brcm,bcm23550 409 - brcm,bcm-nsp-smp 410 # and if enable-method is present 411 required: 412 - enable-method 413 then: 414 required: 415 - secondary-boot-reg 416 - if: 417 properties: 418 enable-method: 419 enum: 420 - spin-table 421 - renesas,r9a06g032-smp 422 required: 423 - enable-method 424 then: 425 required: 426 - cpu-release-addr 427 - if: 428 properties: 429 enable-method: 430 enum: 431 - qcom,kpss-acc-v1 432 - qcom,kpss-acc-v2 433 - qcom,msm8226-smp 434 - qcom,msm8916-smp 435 required: 436 - enable-method 437 then: 438 required: 439 - qcom,acc 440 - qcom,saw 441 else: 442 if: 443 # 2 Qualcomm platforms bootloaders need qcom,acc and qcom,saw yet use 444 # "spin-table" or "psci" enable-methods. Disallowing the properties for 445 # all other CPUs is the best we can do as there's not any way to 446 # distinguish these Qualcomm platforms. 447 not: 448 properties: 449 compatible: 450 const: arm,cortex-a53 451 then: 452 properties: 453 qcom,acc: false 454 qcom,saw: false 455 456required: 457 - device_type 458 - reg 459 - compatible 460 461dependencies: 462 rockchip,pmu: [enable-method] 463 464unevaluatedProperties: false 465 466examples: 467 - | 468 cpus { 469 #size-cells = <0>; 470 #address-cells = <1>; 471 472 cpu@0 { 473 device_type = "cpu"; 474 compatible = "arm,cortex-a15"; 475 reg = <0x0>; 476 }; 477 478 cpu@1 { 479 device_type = "cpu"; 480 compatible = "arm,cortex-a15"; 481 reg = <0x1>; 482 }; 483 484 cpu@100 { 485 device_type = "cpu"; 486 compatible = "arm,cortex-a7"; 487 reg = <0x100>; 488 }; 489 490 cpu@101 { 491 device_type = "cpu"; 492 compatible = "arm,cortex-a7"; 493 reg = <0x101>; 494 }; 495 }; 496 497 - | 498 // Example 2 (Cortex-A8 uniprocessor 32-bit system): 499 cpus { 500 #size-cells = <0>; 501 #address-cells = <1>; 502 503 cpu@0 { 504 device_type = "cpu"; 505 compatible = "arm,cortex-a8"; 506 reg = <0x0>; 507 }; 508 }; 509 510 - | 511 // Example 3 (ARM 926EJ-S uniprocessor 32-bit system): 512 cpus { 513 #size-cells = <0>; 514 #address-cells = <1>; 515 516 cpu@0 { 517 device_type = "cpu"; 518 compatible = "arm,arm926ej-s"; 519 reg = <0x0>; 520 }; 521 }; 522 523 - | 524 // Example 4 (ARM Cortex-A57 64-bit system): 525 cpus { 526 #size-cells = <0>; 527 #address-cells = <2>; 528 529 cpu@0 { 530 device_type = "cpu"; 531 compatible = "arm,cortex-a57"; 532 reg = <0x0 0x0>; 533 enable-method = "spin-table"; 534 cpu-release-addr = <0 0x20000000>; 535 }; 536 537 cpu@1 { 538 device_type = "cpu"; 539 compatible = "arm,cortex-a57"; 540 reg = <0x0 0x1>; 541 enable-method = "spin-table"; 542 cpu-release-addr = <0 0x20000000>; 543 }; 544 545 cpu@100 { 546 device_type = "cpu"; 547 compatible = "arm,cortex-a57"; 548 reg = <0x0 0x100>; 549 enable-method = "spin-table"; 550 cpu-release-addr = <0 0x20000000>; 551 }; 552 553 cpu@101 { 554 device_type = "cpu"; 555 compatible = "arm,cortex-a57"; 556 reg = <0x0 0x101>; 557 enable-method = "spin-table"; 558 cpu-release-addr = <0 0x20000000>; 559 }; 560 561 cpu@10000 { 562 device_type = "cpu"; 563 compatible = "arm,cortex-a57"; 564 reg = <0x0 0x10000>; 565 enable-method = "spin-table"; 566 cpu-release-addr = <0 0x20000000>; 567 }; 568 569 cpu@10001 { 570 device_type = "cpu"; 571 compatible = "arm,cortex-a57"; 572 reg = <0x0 0x10001>; 573 enable-method = "spin-table"; 574 cpu-release-addr = <0 0x20000000>; 575 }; 576 577 cpu@10100 { 578 device_type = "cpu"; 579 compatible = "arm,cortex-a57"; 580 reg = <0x0 0x10100>; 581 enable-method = "spin-table"; 582 cpu-release-addr = <0 0x20000000>; 583 }; 584 585 cpu@10101 { 586 device_type = "cpu"; 587 compatible = "arm,cortex-a57"; 588 reg = <0x0 0x10101>; 589 enable-method = "spin-table"; 590 cpu-release-addr = <0 0x20000000>; 591 }; 592 593 cpu@100000000 { 594 device_type = "cpu"; 595 compatible = "arm,cortex-a57"; 596 reg = <0x1 0x0>; 597 enable-method = "spin-table"; 598 cpu-release-addr = <0 0x20000000>; 599 }; 600 601 cpu@100000001 { 602 device_type = "cpu"; 603 compatible = "arm,cortex-a57"; 604 reg = <0x1 0x1>; 605 enable-method = "spin-table"; 606 cpu-release-addr = <0 0x20000000>; 607 }; 608 609 cpu@100000100 { 610 device_type = "cpu"; 611 compatible = "arm,cortex-a57"; 612 reg = <0x1 0x100>; 613 enable-method = "spin-table"; 614 cpu-release-addr = <0 0x20000000>; 615 }; 616 617 cpu@100000101 { 618 device_type = "cpu"; 619 compatible = "arm,cortex-a57"; 620 reg = <0x1 0x101>; 621 enable-method = "spin-table"; 622 cpu-release-addr = <0 0x20000000>; 623 }; 624 625 cpu@100010000 { 626 device_type = "cpu"; 627 compatible = "arm,cortex-a57"; 628 reg = <0x1 0x10000>; 629 enable-method = "spin-table"; 630 cpu-release-addr = <0 0x20000000>; 631 }; 632 633 cpu@100010001 { 634 device_type = "cpu"; 635 compatible = "arm,cortex-a57"; 636 reg = <0x1 0x10001>; 637 enable-method = "spin-table"; 638 cpu-release-addr = <0 0x20000000>; 639 }; 640 641 cpu@100010100 { 642 device_type = "cpu"; 643 compatible = "arm,cortex-a57"; 644 reg = <0x1 0x10100>; 645 enable-method = "spin-table"; 646 cpu-release-addr = <0 0x20000000>; 647 }; 648 649 cpu@100010101 { 650 device_type = "cpu"; 651 compatible = "arm,cortex-a57"; 652 reg = <0x1 0x10101>; 653 enable-method = "spin-table"; 654 cpu-release-addr = <0 0x20000000>; 655 }; 656 }; 657... 658