xref: /linux/Documentation/devicetree/bindings/arm/cpus.yaml (revision 223981db9bafb80f558162c148f261e2ff043dbe)
1# SPDX-License-Identifier: GPL-2.0
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/arm/cpus.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: ARM CPUs
8
9maintainers:
10  - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
11
12description: |+
13  The device tree allows to describe the layout of CPUs in a system through
14  the "cpus" node, which in turn contains a number of subnodes (ie "cpu")
15  defining properties for every cpu.
16
17  Bindings for CPU nodes follow the Devicetree Specification, available from:
18
19  https://www.devicetree.org/specifications/
20
21  with updates for 32-bit and 64-bit ARM systems provided in this document.
22
23  ================================
24  Convention used in this document
25  ================================
26
27  This document follows the conventions described in the Devicetree
28  Specification, with the addition:
29
30  - square brackets define bitfields, eg reg[7:0] value of the bitfield in
31    the reg property contained in bits 7 down to 0
32
33  =====================================
34  cpus and cpu node bindings definition
35  =====================================
36
37  The ARM architecture, in accordance with the Devicetree Specification,
38  requires the cpus and cpu nodes to be present and contain the properties
39  described below.
40
41properties:
42  reg:
43    maxItems: 1
44    description: |
45      Usage and definition depend on ARM architecture version and
46      configuration:
47
48      On uniprocessor ARM architectures previous to v7
49      this property is required and must be set to 0.
50
51      On ARM 11 MPcore based systems this property is
52        required and matches the CPUID[11:0] register bits.
53
54        Bits [11:0] in the reg cell must be set to
55        bits [11:0] in CPU ID register.
56
57        All other bits in the reg cell must be set to 0.
58
59      On 32-bit ARM v7 or later systems this property is
60        required and matches the CPU MPIDR[23:0] register
61        bits.
62
63        Bits [23:0] in the reg cell must be set to
64        bits [23:0] in MPIDR.
65
66        All other bits in the reg cell must be set to 0.
67
68      On ARM v8 64-bit systems this property is required
69        and matches the MPIDR_EL1 register affinity bits.
70
71        * If cpus node's #address-cells property is set to 2
72
73          The first reg cell bits [7:0] must be set to
74          bits [39:32] of MPIDR_EL1.
75
76          The second reg cell bits [23:0] must be set to
77          bits [23:0] of MPIDR_EL1.
78
79        * If cpus node's #address-cells property is set to 1
80
81          The reg cell bits [23:0] must be set to bits [23:0]
82          of MPIDR_EL1.
83
84      All other bits in the reg cells must be set to 0.
85
86  compatible:
87    enum:
88      - apple,avalanche
89      - apple,blizzard
90      - apple,icestorm
91      - apple,firestorm
92      - arm,arm710t
93      - arm,arm720t
94      - arm,arm740t
95      - arm,arm7ej-s
96      - arm,arm7tdmi
97      - arm,arm7tdmi-s
98      - arm,arm9es
99      - arm,arm9ej-s
100      - arm,arm920t
101      - arm,arm922t
102      - arm,arm925
103      - arm,arm926e-s
104      - arm,arm926ej-s
105      - arm,arm940t
106      - arm,arm946e-s
107      - arm,arm966e-s
108      - arm,arm968e-s
109      - arm,arm9tdmi
110      - arm,arm1020e
111      - arm,arm1020t
112      - arm,arm1022e
113      - arm,arm1026ej-s
114      - arm,arm1136j-s
115      - arm,arm1136jf-s
116      - arm,arm1156t2-s
117      - arm,arm1156t2f-s
118      - arm,arm1176jzf
119      - arm,arm1176jz-s
120      - arm,arm1176jzf-s
121      - arm,arm11mpcore
122      - arm,armv8 # Only for s/w models
123      - arm,cortex-a5
124      - arm,cortex-a7
125      - arm,cortex-a8
126      - arm,cortex-a9
127      - arm,cortex-a12
128      - arm,cortex-a15
129      - arm,cortex-a17
130      - arm,cortex-a32
131      - arm,cortex-a34
132      - arm,cortex-a35
133      - arm,cortex-a53
134      - arm,cortex-a55
135      - arm,cortex-a57
136      - arm,cortex-a65
137      - arm,cortex-a72
138      - arm,cortex-a73
139      - arm,cortex-a75
140      - arm,cortex-a76
141      - arm,cortex-a77
142      - arm,cortex-a78
143      - arm,cortex-a78ae
144      - arm,cortex-a78c
145      - arm,cortex-a510
146      - arm,cortex-a520
147      - arm,cortex-a710
148      - arm,cortex-a715
149      - arm,cortex-a720
150      - arm,cortex-m0
151      - arm,cortex-m0+
152      - arm,cortex-m1
153      - arm,cortex-m3
154      - arm,cortex-m4
155      - arm,cortex-r4
156      - arm,cortex-r5
157      - arm,cortex-r7
158      - arm,cortex-r52
159      - arm,cortex-x1
160      - arm,cortex-x1c
161      - arm,cortex-x2
162      - arm,cortex-x3
163      - arm,cortex-x4
164      - arm,neoverse-e1
165      - arm,neoverse-n1
166      - arm,neoverse-n2
167      - arm,neoverse-v1
168      - brcm,brahma-b15
169      - brcm,brahma-b53
170      - brcm,vulcan
171      - cavium,thunder
172      - cavium,thunder2
173      - faraday,fa526
174      - intel,sa110
175      - intel,sa1100
176      - marvell,feroceon
177      - marvell,mohawk
178      - marvell,pj4a
179      - marvell,pj4b
180      - marvell,sheeva-v5
181      - marvell,sheeva-v7
182      - nvidia,tegra132-denver
183      - nvidia,tegra186-denver
184      - nvidia,tegra194-carmel
185      - qcom,krait
186      - qcom,kryo
187      - qcom,kryo240
188      - qcom,kryo250
189      - qcom,kryo260
190      - qcom,kryo280
191      - qcom,kryo360
192      - qcom,kryo385
193      - qcom,kryo465
194      - qcom,kryo468
195      - qcom,kryo485
196      - qcom,kryo560
197      - qcom,kryo570
198      - qcom,kryo660
199      - qcom,kryo685
200      - qcom,kryo780
201      - qcom,scorpion
202
203  enable-method:
204    $ref: /schemas/types.yaml#/definitions/string
205    oneOf:
206      # On ARM v8 64-bit this property is required
207      - enum:
208          - psci
209          - spin-table
210      # On ARM 32-bit systems this property is optional
211      - enum:
212          - actions,s500-smp
213          - allwinner,sun6i-a31
214          - allwinner,sun8i-a23
215          - allwinner,sun9i-a80-smp
216          - allwinner,sun8i-a83t-smp
217          - amlogic,meson8-smp
218          - amlogic,meson8b-smp
219          - arm,realview-smp
220          - aspeed,ast2600-smp
221          - brcm,bcm11351-cpu-method
222          - brcm,bcm23550
223          - brcm,bcm2836-smp
224          - brcm,bcm63138
225          - brcm,bcm-nsp-smp
226          - brcm,brahma-b15
227          - marvell,armada-375-smp
228          - marvell,armada-380-smp
229          - marvell,armada-390-smp
230          - marvell,armada-xp-smp
231          - marvell,98dx3236-smp
232          - marvell,mmp3-smp
233          - mediatek,mt6589-smp
234          - mediatek,mt81xx-tz-smp
235          - qcom,gcc-msm8660
236          - qcom,kpss-acc-v1
237          - qcom,kpss-acc-v2
238          - qcom,msm8226-smp
239          - qcom,msm8909-smp
240          # Only valid on ARM 32-bit, see above for ARM v8 64-bit
241          - qcom,msm8916-smp
242          - renesas,apmu
243          - renesas,r9a06g032-smp
244          - rockchip,rk3036-smp
245          - rockchip,rk3066-smp
246          - socionext,milbeaut-m10v-smp
247          - ste,dbx500-smp
248          - ti,am3352
249          - ti,am4372
250
251  cpu-release-addr:
252    oneOf:
253      - $ref: /schemas/types.yaml#/definitions/uint32
254      - $ref: /schemas/types.yaml#/definitions/uint64
255    description:
256      The DT specification defines this as 64-bit always, but some 32-bit Arm
257      systems have used a 32-bit value which must be supported.
258      Required for systems that have an "enable-method"
259        property value of "spin-table".
260
261  cpu-idle-states:
262    $ref: /schemas/types.yaml#/definitions/phandle-array
263    items:
264      maxItems: 1
265    description: |
266      List of phandles to idle state nodes supported
267      by this cpu (see ./idle-states.yaml).
268
269  capacity-dmips-mhz:
270    description:
271      u32 value representing CPU capacity (see ../cpu/cpu-capacity.txt) in
272      DMIPS/MHz, relative to highest capacity-dmips-mhz
273      in the system.
274
275  cci-control-port: true
276
277  dynamic-power-coefficient:
278    $ref: /schemas/types.yaml#/definitions/uint32
279    description:
280      A u32 value that represents the running time dynamic
281      power coefficient in units of uW/MHz/V^2. The
282      coefficient can either be calculated from power
283      measurements or derived by analysis.
284
285      The dynamic power consumption of the CPU  is
286      proportional to the square of the Voltage (V) and
287      the clock frequency (f). The coefficient is used to
288      calculate the dynamic power as below -
289
290      Pdyn = dynamic-power-coefficient * V^2 * f
291
292      where voltage is in V, frequency is in MHz.
293
294  performance-domains:
295    maxItems: 1
296    description:
297      List of phandles and performance domain specifiers, as defined by
298      bindings of the performance domain provider. See also
299      dvfs/performance-domain.yaml.
300
301  power-domains:
302    description:
303      List of phandles and PM domain specifiers, as defined by bindings of the
304      PM domain provider (see also ../power_domain.txt).
305
306  power-domain-names:
307    description:
308      A list of power domain name strings sorted in the same order as the
309      power-domains property.
310
311      For PSCI based platforms, the name corresponding to the index of the PSCI
312      PM domain provider, must be "psci". For SCMI based platforms, the name
313      corresponding to the index of an SCMI performance domain provider, must be
314      "perf".
315
316  qcom,saw:
317    $ref: /schemas/types.yaml#/definitions/phandle
318    description: |
319      Specifies the SAW* node associated with this CPU.
320
321      Required for systems that have an "enable-method" property
322      value of "qcom,kpss-acc-v1" or "qcom,kpss-acc-v2"
323
324      * arm/msm/qcom,saw2.txt
325
326  qcom,acc:
327    $ref: /schemas/types.yaml#/definitions/phandle
328    description: |
329      Specifies the ACC* node associated with this CPU.
330
331      Required for systems that have an "enable-method" property
332      value of "qcom,kpss-acc-v1", "qcom,kpss-acc-v2", "qcom,msm8226-smp" or
333      "qcom,msm8916-smp".
334
335      * arm/msm/qcom,kpss-acc.txt
336
337  rockchip,pmu:
338    $ref: /schemas/types.yaml#/definitions/phandle
339    description: |
340      Specifies the syscon node controlling the cpu core power domains.
341
342      Optional for systems that have an "enable-method"
343      property value of "rockchip,rk3066-smp"
344      While optional, it is the preferred way to get access to
345      the cpu-core power-domains.
346
347  secondary-boot-reg:
348    $ref: /schemas/types.yaml#/definitions/uint32
349    description: |
350      Required for systems that have an "enable-method" property value of
351      "brcm,bcm11351-cpu-method", "brcm,bcm23550" or "brcm,bcm-nsp-smp".
352
353      This includes the following SoCs: |
354      BCM11130, BCM11140, BCM11351, BCM28145, BCM28155, BCM21664, BCM23550
355      BCM58522, BCM58525, BCM58535, BCM58622, BCM58623, BCM58625, BCM88312
356
357      The secondary-boot-reg property is a u32 value that specifies the
358      physical address of the register used to request the ROM holding pen
359      code release a secondary CPU. The value written to the register is
360      formed by encoding the target CPU id into the low bits of the
361      physical start address it should jump to.
362
363if:
364  # If the enable-method property contains one of those values
365  properties:
366    enable-method:
367      contains:
368        enum:
369          - brcm,bcm11351-cpu-method
370          - brcm,bcm23550
371          - brcm,bcm-nsp-smp
372  # and if enable-method is present
373  required:
374    - enable-method
375
376then:
377  required:
378    - secondary-boot-reg
379
380required:
381  - device_type
382  - reg
383  - compatible
384
385dependencies:
386  rockchip,pmu: [enable-method]
387
388additionalProperties: true
389
390examples:
391  - |
392    cpus {
393      #size-cells = <0>;
394      #address-cells = <1>;
395
396      cpu@0 {
397        device_type = "cpu";
398        compatible = "arm,cortex-a15";
399        reg = <0x0>;
400      };
401
402      cpu@1 {
403        device_type = "cpu";
404        compatible = "arm,cortex-a15";
405        reg = <0x1>;
406      };
407
408      cpu@100 {
409        device_type = "cpu";
410        compatible = "arm,cortex-a7";
411        reg = <0x100>;
412      };
413
414      cpu@101 {
415        device_type = "cpu";
416        compatible = "arm,cortex-a7";
417        reg = <0x101>;
418      };
419    };
420
421  - |
422    // Example 2 (Cortex-A8 uniprocessor 32-bit system):
423    cpus {
424      #size-cells = <0>;
425      #address-cells = <1>;
426
427      cpu@0 {
428        device_type = "cpu";
429        compatible = "arm,cortex-a8";
430        reg = <0x0>;
431      };
432    };
433
434  - |
435    // Example 3 (ARM 926EJ-S uniprocessor 32-bit system):
436    cpus {
437      #size-cells = <0>;
438      #address-cells = <1>;
439
440      cpu@0 {
441        device_type = "cpu";
442        compatible = "arm,arm926ej-s";
443        reg = <0x0>;
444      };
445    };
446
447  - |
448    //  Example 4 (ARM Cortex-A57 64-bit system):
449    cpus {
450      #size-cells = <0>;
451      #address-cells = <2>;
452
453      cpu@0 {
454        device_type = "cpu";
455        compatible = "arm,cortex-a57";
456        reg = <0x0 0x0>;
457        enable-method = "spin-table";
458        cpu-release-addr = <0 0x20000000>;
459      };
460
461      cpu@1 {
462        device_type = "cpu";
463        compatible = "arm,cortex-a57";
464        reg = <0x0 0x1>;
465        enable-method = "spin-table";
466        cpu-release-addr = <0 0x20000000>;
467      };
468
469      cpu@100 {
470        device_type = "cpu";
471        compatible = "arm,cortex-a57";
472        reg = <0x0 0x100>;
473        enable-method = "spin-table";
474        cpu-release-addr = <0 0x20000000>;
475      };
476
477      cpu@101 {
478        device_type = "cpu";
479        compatible = "arm,cortex-a57";
480        reg = <0x0 0x101>;
481        enable-method = "spin-table";
482        cpu-release-addr = <0 0x20000000>;
483      };
484
485      cpu@10000 {
486        device_type = "cpu";
487        compatible = "arm,cortex-a57";
488        reg = <0x0 0x10000>;
489        enable-method = "spin-table";
490        cpu-release-addr = <0 0x20000000>;
491      };
492
493      cpu@10001 {
494        device_type = "cpu";
495        compatible = "arm,cortex-a57";
496        reg = <0x0 0x10001>;
497        enable-method = "spin-table";
498        cpu-release-addr = <0 0x20000000>;
499      };
500
501      cpu@10100 {
502        device_type = "cpu";
503        compatible = "arm,cortex-a57";
504        reg = <0x0 0x10100>;
505        enable-method = "spin-table";
506        cpu-release-addr = <0 0x20000000>;
507      };
508
509      cpu@10101 {
510        device_type = "cpu";
511        compatible = "arm,cortex-a57";
512        reg = <0x0 0x10101>;
513        enable-method = "spin-table";
514        cpu-release-addr = <0 0x20000000>;
515      };
516
517      cpu@100000000 {
518        device_type = "cpu";
519        compatible = "arm,cortex-a57";
520        reg = <0x1 0x0>;
521        enable-method = "spin-table";
522        cpu-release-addr = <0 0x20000000>;
523      };
524
525      cpu@100000001 {
526        device_type = "cpu";
527        compatible = "arm,cortex-a57";
528        reg = <0x1 0x1>;
529        enable-method = "spin-table";
530        cpu-release-addr = <0 0x20000000>;
531      };
532
533      cpu@100000100 {
534        device_type = "cpu";
535        compatible = "arm,cortex-a57";
536        reg = <0x1 0x100>;
537        enable-method = "spin-table";
538        cpu-release-addr = <0 0x20000000>;
539      };
540
541      cpu@100000101 {
542        device_type = "cpu";
543        compatible = "arm,cortex-a57";
544        reg = <0x1 0x101>;
545        enable-method = "spin-table";
546        cpu-release-addr = <0 0x20000000>;
547      };
548
549      cpu@100010000 {
550        device_type = "cpu";
551        compatible = "arm,cortex-a57";
552        reg = <0x1 0x10000>;
553        enable-method = "spin-table";
554        cpu-release-addr = <0 0x20000000>;
555      };
556
557      cpu@100010001 {
558        device_type = "cpu";
559        compatible = "arm,cortex-a57";
560        reg = <0x1 0x10001>;
561        enable-method = "spin-table";
562        cpu-release-addr = <0 0x20000000>;
563      };
564
565      cpu@100010100 {
566        device_type = "cpu";
567        compatible = "arm,cortex-a57";
568        reg = <0x1 0x10100>;
569        enable-method = "spin-table";
570        cpu-release-addr = <0 0x20000000>;
571      };
572
573      cpu@100010101 {
574        device_type = "cpu";
575        compatible = "arm,cortex-a57";
576        reg = <0x1 0x10101>;
577        enable-method = "spin-table";
578        cpu-release-addr = <0 0x20000000>;
579      };
580    };
581...
582