xref: /linux/Documentation/devicetree/bindings/arm/cpu-enable-method/nuvoton,npcm750-smp (revision c1144d29f405ce1f4e6ede6482beb3d0d09750c6)
1*d6bdd009SBrendan Higgins=========================================================
2*d6bdd009SBrendan HigginsSecondary CPU enable-method "nuvoton,npcm750-smp" binding
3*d6bdd009SBrendan Higgins=========================================================
4*d6bdd009SBrendan Higgins
5*d6bdd009SBrendan HigginsTo apply to all CPUs, a single "nuvoton,npcm750-smp" enable method should be
6*d6bdd009SBrendan Higginsdefined in the "cpus" node.
7*d6bdd009SBrendan Higgins
8*d6bdd009SBrendan HigginsEnable method name:	"nuvoton,npcm750-smp"
9*d6bdd009SBrendan HigginsCompatible machines:	"nuvoton,npcm750"
10*d6bdd009SBrendan HigginsCompatible CPUs:	"arm,cortex-a9"
11*d6bdd009SBrendan HigginsRelated properties:	(none)
12*d6bdd009SBrendan Higgins
13*d6bdd009SBrendan HigginsNote:
14*d6bdd009SBrendan HigginsThis enable method needs valid nodes compatible with "arm,cortex-a9-scu" and
15*d6bdd009SBrendan Higgins"nuvoton,npcm750-gcr".
16*d6bdd009SBrendan Higgins
17*d6bdd009SBrendan HigginsExample:
18*d6bdd009SBrendan Higgins
19*d6bdd009SBrendan Higgins	cpus {
20*d6bdd009SBrendan Higgins		#address-cells = <1>;
21*d6bdd009SBrendan Higgins		#size-cells = <0>;
22*d6bdd009SBrendan Higgins		enable-method = "nuvoton,npcm750-smp";
23*d6bdd009SBrendan Higgins
24*d6bdd009SBrendan Higgins		cpu@0 {
25*d6bdd009SBrendan Higgins			device_type = "cpu";
26*d6bdd009SBrendan Higgins			compatible = "arm,cortex-a9";
27*d6bdd009SBrendan Higgins			clocks = <&clk NPCM7XX_CLK_CPU>;
28*d6bdd009SBrendan Higgins			clock-names = "clk_cpu";
29*d6bdd009SBrendan Higgins			reg = <0>;
30*d6bdd009SBrendan Higgins			next-level-cache = <&L2>;
31*d6bdd009SBrendan Higgins		};
32*d6bdd009SBrendan Higgins
33*d6bdd009SBrendan Higgins		cpu@1 {
34*d6bdd009SBrendan Higgins			device_type = "cpu";
35*d6bdd009SBrendan Higgins			compatible = "arm,cortex-a9";
36*d6bdd009SBrendan Higgins			clocks = <&clk NPCM7XX_CLK_CPU>;
37*d6bdd009SBrendan Higgins			clock-names = "clk_cpu";
38*d6bdd009SBrendan Higgins			reg = <1>;
39*d6bdd009SBrendan Higgins			next-level-cache = <&L2>;
40*d6bdd009SBrendan Higgins		};
41*d6bdd009SBrendan Higgins	};
42*d6bdd009SBrendan Higgins
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