1*4b989e6eSAryabhatta Dey# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*4b989e6eSAryabhatta Dey%YAML 1.2 3*4b989e6eSAryabhatta Dey--- 4*4b989e6eSAryabhatta Dey$id: http://devicetree.org/schemas/arc/snps,archs-pct.yaml# 5*4b989e6eSAryabhatta Dey$schema: http://devicetree.org/meta-schemas/core.yaml# 6*4b989e6eSAryabhatta Dey 7*4b989e6eSAryabhatta Deytitle: ARC HS Performance Counters 8*4b989e6eSAryabhatta Dey 9*4b989e6eSAryabhatta Deymaintainers: 10*4b989e6eSAryabhatta Dey - Aryabhatta Dey <aryabhattadey35@gmail.com> 11*4b989e6eSAryabhatta Dey 12*4b989e6eSAryabhatta Deydescription: 13*4b989e6eSAryabhatta Dey The ARC HS can be configured with a pipeline performance monitor for counting 14*4b989e6eSAryabhatta Dey CPU and cache events like cache misses and hits. Like conventional PCT there 15*4b989e6eSAryabhatta Dey are 100+ hardware conditions dynamically mapped to up to 32 counters. 16*4b989e6eSAryabhatta Dey It also supports overflow interrupts. 17*4b989e6eSAryabhatta Dey 18*4b989e6eSAryabhatta Deyproperties: 19*4b989e6eSAryabhatta Dey compatible: 20*4b989e6eSAryabhatta Dey const: snps,archs-pct 21*4b989e6eSAryabhatta Dey 22*4b989e6eSAryabhatta Dey reg: 23*4b989e6eSAryabhatta Dey maxItems: 1 24*4b989e6eSAryabhatta Dey 25*4b989e6eSAryabhatta Dey clocks: 26*4b989e6eSAryabhatta Dey maxItems: 1 27*4b989e6eSAryabhatta Dey 28*4b989e6eSAryabhatta Deyrequired: 29*4b989e6eSAryabhatta Dey - compatible 30*4b989e6eSAryabhatta Dey - reg 31*4b989e6eSAryabhatta Dey - clocks 32*4b989e6eSAryabhatta Dey 33*4b989e6eSAryabhatta DeyadditionalProperties: false 34