1.. contents:: 2.. sectnum:: 3 4====================================== 5BPF Instruction Set Architecture (ISA) 6====================================== 7 8eBPF (which is no longer an acronym for anything), also commonly 9referred to as BPF, is a technology with origins in the Linux kernel 10that can run untrusted programs in a privileged context such as an 11operating system kernel. This document specifies the BPF instruction 12set architecture (ISA). 13 14Documentation conventions 15========================= 16 17The key words "MUST", "MUST NOT", "REQUIRED", "SHALL", "SHALL NOT", 18"SHOULD", "SHOULD NOT", "RECOMMENDED", "NOT RECOMMENDED", "MAY", and 19"OPTIONAL" in this document are to be interpreted as described in 20BCP 14 `<https://www.rfc-editor.org/info/rfc2119>`_ 21`RFC8174 <https://www.rfc-editor.org/info/rfc8174>`_ 22when, and only when, they appear in all capitals, as shown here. 23 24For brevity and consistency, this document refers to families 25of types using a shorthand syntax and refers to several expository, 26mnemonic functions when describing the semantics of instructions. 27The range of valid values for those types and the semantics of those 28functions are defined in the following subsections. 29 30Types 31----- 32This document refers to integer types with the notation `SN` to specify 33a type's signedness (`S`) and bit width (`N`), respectively. 34 35.. table:: Meaning of signedness notation. 36 37 ==== ========= 38 S Meaning 39 ==== ========= 40 u unsigned 41 s signed 42 ==== ========= 43 44.. table:: Meaning of bit-width notation. 45 46 ===== ========= 47 N Bit width 48 ===== ========= 49 8 8 bits 50 16 16 bits 51 32 32 bits 52 64 64 bits 53 128 128 bits 54 ===== ========= 55 56For example, `u32` is a type whose valid values are all the 32-bit unsigned 57numbers and `s16` is a type whose valid values are all the 16-bit signed 58numbers. 59 60Functions 61--------- 62* htobe16: Takes an unsigned 16-bit number in host-endian format and 63 returns the equivalent number as an unsigned 16-bit number in big-endian 64 format. 65* htobe32: Takes an unsigned 32-bit number in host-endian format and 66 returns the equivalent number as an unsigned 32-bit number in big-endian 67 format. 68* htobe64: Takes an unsigned 64-bit number in host-endian format and 69 returns the equivalent number as an unsigned 64-bit number in big-endian 70 format. 71* htole16: Takes an unsigned 16-bit number in host-endian format and 72 returns the equivalent number as an unsigned 16-bit number in little-endian 73 format. 74* htole32: Takes an unsigned 32-bit number in host-endian format and 75 returns the equivalent number as an unsigned 32-bit number in little-endian 76 format. 77* htole64: Takes an unsigned 64-bit number in host-endian format and 78 returns the equivalent number as an unsigned 64-bit number in little-endian 79 format. 80* bswap16: Takes an unsigned 16-bit number in either big- or little-endian 81 format and returns the equivalent number with the same bit width but 82 opposite endianness. 83* bswap32: Takes an unsigned 32-bit number in either big- or little-endian 84 format and returns the equivalent number with the same bit width but 85 opposite endianness. 86* bswap64: Takes an unsigned 64-bit number in either big- or little-endian 87 format and returns the equivalent number with the same bit width but 88 opposite endianness. 89 90 91Definitions 92----------- 93 94.. glossary:: 95 96 Sign Extend 97 To `sign extend an` ``X`` `-bit number, A, to a` ``Y`` `-bit number, B ,` means to 98 99 #. Copy all ``X`` bits from `A` to the lower ``X`` bits of `B`. 100 #. Set the value of the remaining ``Y`` - ``X`` bits of `B` to the value of 101 the most-significant bit of `A`. 102 103.. admonition:: Example 104 105 Sign extend an 8-bit number ``A`` to a 16-bit number ``B`` on a big-endian platform: 106 :: 107 108 A: 10000110 109 B: 11111111 10000110 110 111Conformance groups 112------------------ 113 114An implementation does not need to support all instructions specified in this 115document (e.g., deprecated instructions). Instead, a number of conformance 116groups are specified. An implementation MUST support the base32 conformance 117group and MAY support additional conformance groups, where supporting a 118conformance group means it MUST support all instructions in that conformance 119group. 120 121The use of named conformance groups enables interoperability between a runtime 122that executes instructions, and tools such as compilers that generate 123instructions for the runtime. Thus, capability discovery in terms of 124conformance groups might be done manually by users or automatically by tools. 125 126Each conformance group has a short ASCII label (e.g., "base32") that 127corresponds to a set of instructions that are mandatory. That is, each 128instruction has one or more conformance groups of which it is a member. 129 130This document defines the following conformance groups: 131 132* base32: includes all instructions defined in this 133 specification unless otherwise noted. 134* base64: includes base32, plus instructions explicitly noted 135 as being in the base64 conformance group. 136* atomic32: includes 32-bit atomic operation instructions (see `Atomic operations`_). 137* atomic64: includes atomic32, plus 64-bit atomic operation instructions. 138* divmul32: includes 32-bit division, multiplication, and modulo instructions. 139* divmul64: includes divmul32, plus 64-bit division, multiplication, 140 and modulo instructions. 141* packet: deprecated packet access instructions. 142 143Instruction encoding 144==================== 145 146BPF has two instruction encodings: 147 148* the basic instruction encoding, which uses 64 bits to encode an instruction 149* the wide instruction encoding, which appends a second 64 bits 150 after the basic instruction for a total of 128 bits. 151 152Basic instruction encoding 153-------------------------- 154 155A basic instruction is encoded as follows:: 156 157 +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 158 | opcode | regs | offset | 159 +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 160 | imm | 161 +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 162 163**opcode** 164 operation to perform, encoded as follows:: 165 166 +-+-+-+-+-+-+-+-+ 167 |specific |class| 168 +-+-+-+-+-+-+-+-+ 169 170 **specific** 171 The format of these bits varies by instruction class 172 173 **class** 174 The instruction class (see `Instruction classes`_) 175 176**regs** 177 The source and destination register numbers, encoded as follows 178 on a little-endian host:: 179 180 +-+-+-+-+-+-+-+-+ 181 |src_reg|dst_reg| 182 +-+-+-+-+-+-+-+-+ 183 184 and as follows on a big-endian host:: 185 186 +-+-+-+-+-+-+-+-+ 187 |dst_reg|src_reg| 188 +-+-+-+-+-+-+-+-+ 189 190 **src_reg** 191 the source register number (0-10), except where otherwise specified 192 (`64-bit immediate instructions`_ reuse this field for other purposes) 193 194 **dst_reg** 195 destination register number (0-10), unless otherwise specified 196 (future instructions might reuse this field for other purposes) 197 198**offset** 199 signed integer offset used with pointer arithmetic, except where 200 otherwise specified (some arithmetic instructions reuse this field 201 for other purposes) 202 203**imm** 204 signed integer immediate value 205 206Note that the contents of multi-byte fields ('offset' and 'imm') are 207stored using big-endian byte ordering on big-endian hosts and 208little-endian byte ordering on little-endian hosts. 209 210For example:: 211 212 opcode offset imm assembly 213 src_reg dst_reg 214 07 0 1 00 00 44 33 22 11 r1 += 0x11223344 // little 215 dst_reg src_reg 216 07 1 0 00 00 11 22 33 44 r1 += 0x11223344 // big 217 218Note that most instructions do not use all of the fields. 219Unused fields SHALL be cleared to zero. 220 221Wide instruction encoding 222-------------------------- 223 224Some instructions are defined to use the wide instruction encoding, 225which uses two 32-bit immediate values. The 64 bits following 226the basic instruction format contain a pseudo instruction 227with 'opcode', 'dst_reg', 'src_reg', and 'offset' all set to zero. 228 229This is depicted in the following figure:: 230 231 +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 232 | opcode | regs | offset | 233 +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 234 | imm | 235 +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 236 | reserved | 237 +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 238 | next_imm | 239 +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 240 241**opcode** 242 operation to perform, encoded as explained above 243 244**regs** 245 The source and destination register numbers (unless otherwise 246 specified), encoded as explained above 247 248**offset** 249 signed integer offset used with pointer arithmetic, unless 250 otherwise specified 251 252**imm** 253 signed integer immediate value 254 255**reserved** 256 unused, set to zero 257 258**next_imm** 259 second signed integer immediate value 260 261Instruction classes 262------------------- 263 264The three least significant bits of the 'opcode' field store the instruction class: 265 266===== ===== =============================== =================================== 267class value description reference 268===== ===== =============================== =================================== 269LD 0x0 non-standard load operations `Load and store instructions`_ 270LDX 0x1 load into register operations `Load and store instructions`_ 271ST 0x2 store from immediate operations `Load and store instructions`_ 272STX 0x3 store from register operations `Load and store instructions`_ 273ALU 0x4 32-bit arithmetic operations `Arithmetic and jump instructions`_ 274JMP 0x5 64-bit jump operations `Arithmetic and jump instructions`_ 275JMP32 0x6 32-bit jump operations `Arithmetic and jump instructions`_ 276ALU64 0x7 64-bit arithmetic operations `Arithmetic and jump instructions`_ 277===== ===== =============================== =================================== 278 279Arithmetic and jump instructions 280================================ 281 282For arithmetic and jump instructions (``ALU``, ``ALU64``, ``JMP`` and 283``JMP32``), the 8-bit 'opcode' field is divided into three parts:: 284 285 +-+-+-+-+-+-+-+-+ 286 | code |s|class| 287 +-+-+-+-+-+-+-+-+ 288 289**code** 290 the operation code, whose meaning varies by instruction class 291 292**s (source)** 293 the source operand location, which unless otherwise specified is one of: 294 295 ====== ===== ============================================== 296 source value description 297 ====== ===== ============================================== 298 K 0 use 32-bit 'imm' value as source operand 299 X 1 use 'src_reg' register value as source operand 300 ====== ===== ============================================== 301 302**instruction class** 303 the instruction class (see `Instruction classes`_) 304 305Arithmetic instructions 306----------------------- 307 308``ALU`` uses 32-bit wide operands while ``ALU64`` uses 64-bit wide operands for 309otherwise identical operations. ``ALU64`` instructions belong to the 310base64 conformance group unless noted otherwise. 311The 'code' field encodes the operation as below, where 'src' refers to the 312the source operand and 'dst' refers to the value of the destination 313register. 314 315===== ===== ======= ========================================================== 316name code offset description 317===== ===== ======= ========================================================== 318ADD 0x0 0 dst += src 319SUB 0x1 0 dst -= src 320MUL 0x2 0 dst \*= src 321DIV 0x3 0 dst = (src != 0) ? (dst / src) : 0 322SDIV 0x3 1 dst = (src != 0) ? (dst s/ src) : 0 323OR 0x4 0 dst \|= src 324AND 0x5 0 dst &= src 325LSH 0x6 0 dst <<= (src & mask) 326RSH 0x7 0 dst >>= (src & mask) 327NEG 0x8 0 dst = -dst 328MOD 0x9 0 dst = (src != 0) ? (dst % src) : dst 329SMOD 0x9 1 dst = (src != 0) ? (dst s% src) : dst 330XOR 0xa 0 dst ^= src 331MOV 0xb 0 dst = src 332MOVSX 0xb 8/16/32 dst = (s8,s16,s32)src 333ARSH 0xc 0 :term:`sign extending<Sign Extend>` dst >>= (src & mask) 334END 0xd 0 byte swap operations (see `Byte swap instructions`_ below) 335===== ===== ======= ========================================================== 336 337Underflow and overflow are allowed during arithmetic operations, meaning 338the 64-bit or 32-bit value will wrap. If BPF program execution would 339result in division by zero, the destination register is instead set to zero. 340If execution would result in modulo by zero, for ``ALU64`` the value of 341the destination register is unchanged whereas for ``ALU`` the upper 34232 bits of the destination register are zeroed. 343 344``{ADD, X, ALU}``, where 'code' = ``ADD``, 'source' = ``X``, and 'class' = ``ALU``, means:: 345 346 dst = (u32) ((u32) dst + (u32) src) 347 348where '(u32)' indicates that the upper 32 bits are zeroed. 349 350``{ADD, X, ALU64}`` means:: 351 352 dst = dst + src 353 354``{XOR, K, ALU}`` means:: 355 356 dst = (u32) dst ^ (u32) imm 357 358``{XOR, K, ALU64}`` means:: 359 360 dst = dst ^ imm 361 362Note that most arithmetic instructions have 'offset' set to 0. Only three instructions 363(``SDIV``, ``SMOD``, ``MOVSX``) have a non-zero 'offset'. 364 365Division, multiplication, and modulo operations for ``ALU`` are part 366of the "divmul32" conformance group, and division, multiplication, and 367modulo operations for ``ALU64`` are part of the "divmul64" conformance 368group. 369The division and modulo operations support both unsigned and signed flavors. 370 371For unsigned operations (``DIV`` and ``MOD``), for ``ALU``, 372'imm' is interpreted as a 32-bit unsigned value. For ``ALU64``, 373'imm' is first :term:`sign extended<Sign Extend>` from 32 to 64 bits, and then 374interpreted as a 64-bit unsigned value. 375 376For signed operations (``SDIV`` and ``SMOD``), for ``ALU``, 377'imm' is interpreted as a 32-bit signed value. For ``ALU64``, 'imm' 378is first :term:`sign extended<Sign Extend>` from 32 to 64 bits, and then 379interpreted as a 64-bit signed value. 380 381Note that there are varying definitions of the signed modulo operation 382when the dividend or divisor are negative, where implementations often 383vary by language such that Python, Ruby, etc. differ from C, Go, Java, 384etc. This specification requires that signed modulo MUST use truncated division 385(where -13 % 3 == -1) as implemented in C, Go, etc.:: 386 387 a % n = a - n * trunc(a / n) 388 389The ``MOVSX`` instruction does a move operation with sign extension. 390``{MOVSX, X, ALU}`` :term:`sign extends<Sign Extend>` 8-bit and 16-bit operands into 39132-bit operands, and zeroes the remaining upper 32 bits. 392``{MOVSX, X, ALU64}`` :term:`sign extends<Sign Extend>` 8-bit, 16-bit, and 32-bit 393operands into 64-bit operands. Unlike other arithmetic instructions, 394``MOVSX`` is only defined for register source operands (``X``). 395 396The ``NEG`` instruction is only defined when the source bit is clear 397(``K``). 398 399Shift operations use a mask of 0x3F (63) for 64-bit operations and 0x1F (31) 400for 32-bit operations. 401 402Byte swap instructions 403---------------------- 404 405The byte swap instructions use instruction classes of ``ALU`` and ``ALU64`` 406and a 4-bit 'code' field of ``END``. 407 408The byte swap instructions operate on the destination register 409only and do not use a separate source register or immediate value. 410 411For ``ALU``, the 1-bit source operand field in the opcode is used to 412select what byte order the operation converts from or to. For 413``ALU64``, the 1-bit source operand field in the opcode is reserved 414and MUST be set to 0. 415 416===== ======== ===== ================================================= 417class source value description 418===== ======== ===== ================================================= 419ALU TO_LE 0 convert between host byte order and little endian 420ALU TO_BE 1 convert between host byte order and big endian 421ALU64 Reserved 0 do byte swap unconditionally 422===== ======== ===== ================================================= 423 424The 'imm' field encodes the width of the swap operations. The following widths 425are supported: 16, 32 and 64. Width 64 operations belong to the base64 426conformance group and other swap operations belong to the base32 427conformance group. 428 429Examples: 430 431``{END, TO_LE, ALU}`` with 'imm' = 16/32/64 means:: 432 433 dst = htole16(dst) 434 dst = htole32(dst) 435 dst = htole64(dst) 436 437``{END, TO_BE, ALU}`` with 'imm' = 16/32/64 means:: 438 439 dst = htobe16(dst) 440 dst = htobe32(dst) 441 dst = htobe64(dst) 442 443``{END, TO_LE, ALU64}`` with 'imm' = 16/32/64 means:: 444 445 dst = bswap16(dst) 446 dst = bswap32(dst) 447 dst = bswap64(dst) 448 449Jump instructions 450----------------- 451 452``JMP32`` uses 32-bit wide operands and indicates the base32 453conformance group, while ``JMP`` uses 64-bit wide operands for 454otherwise identical operations, and indicates the base64 conformance 455group unless otherwise specified. 456The 'code' field encodes the operation as below: 457 458======== ===== ======= ================================= =================================================== 459code value src_reg description notes 460======== ===== ======= ================================= =================================================== 461JA 0x0 0x0 PC += offset {JA, K, JMP} only 462JA 0x0 0x0 PC += imm {JA, K, JMP32} only 463JEQ 0x1 any PC += offset if dst == src 464JGT 0x2 any PC += offset if dst > src unsigned 465JGE 0x3 any PC += offset if dst >= src unsigned 466JSET 0x4 any PC += offset if dst & src 467JNE 0x5 any PC += offset if dst != src 468JSGT 0x6 any PC += offset if dst > src signed 469JSGE 0x7 any PC += offset if dst >= src signed 470CALL 0x8 0x0 call helper function by static ID {CALL, K, JMP} only, see `Helper functions`_ 471CALL 0x8 0x1 call PC += imm {CALL, K, JMP} only, see `Program-local functions`_ 472CALL 0x8 0x2 call helper function by BTF ID {CALL, K, JMP} only, see `Helper functions`_ 473EXIT 0x9 0x0 return {CALL, K, JMP} only 474JLT 0xa any PC += offset if dst < src unsigned 475JLE 0xb any PC += offset if dst <= src unsigned 476JSLT 0xc any PC += offset if dst < src signed 477JSLE 0xd any PC += offset if dst <= src signed 478======== ===== ======= ================================= =================================================== 479 480where 'PC' denotes the program counter, and the offset to increment by 481is in units of 64-bit instructions relative to the instruction following 482the jump instruction. Thus 'PC += 1' skips execution of the next 483instruction if it's a basic instruction or results in undefined behavior 484if the next instruction is a 128-bit wide instruction. 485 486Example: 487 488``{JSGE, X, JMP32}`` means:: 489 490 if (s32)dst s>= (s32)src goto +offset 491 492where 's>=' indicates a signed '>=' comparison. 493 494``{JA, K, JMP32}`` means:: 495 496 gotol +imm 497 498where 'imm' means the branch offset comes from the 'imm' field. 499 500Note that there are two flavors of ``JA`` instructions. The 501``JMP`` class permits a 16-bit jump offset specified by the 'offset' 502field, whereas the ``JMP32`` class permits a 32-bit jump offset 503specified by the 'imm' field. A > 16-bit conditional jump may be 504converted to a < 16-bit conditional jump plus a 32-bit unconditional 505jump. 506 507All ``CALL`` and ``JA`` instructions belong to the 508base32 conformance group. 509 510Helper functions 511~~~~~~~~~~~~~~~~ 512 513Helper functions are a concept whereby BPF programs can call into a 514set of function calls exposed by the underlying platform. 515 516Historically, each helper function was identified by a static ID 517encoded in the 'imm' field. The available helper functions may differ 518for each program type, but static IDs are unique across all program types. 519 520Platforms that support the BPF Type Format (BTF) support identifying 521a helper function by a BTF ID encoded in the 'imm' field, where the BTF ID 522identifies the helper name and type. Further documentation of BTF 523is outside the scope of this document and is left for future work. 524 525Program-local functions 526~~~~~~~~~~~~~~~~~~~~~~~ 527Program-local functions are functions exposed by the same BPF program as the 528caller, and are referenced by offset from the call instruction, similar to 529``JA``. The offset is encoded in the 'imm' field of the call instruction. 530An ``EXIT`` within the program-local function will return to the caller. 531 532Load and store instructions 533=========================== 534 535For load and store instructions (``LD``, ``LDX``, ``ST``, and ``STX``), the 5368-bit 'opcode' field is divided as follows:: 537 538 +-+-+-+-+-+-+-+-+ 539 |mode |sz |class| 540 +-+-+-+-+-+-+-+-+ 541 542**mode** 543 The mode modifier is one of: 544 545 ============= ===== ==================================== ============= 546 mode modifier value description reference 547 ============= ===== ==================================== ============= 548 IMM 0 64-bit immediate instructions `64-bit immediate instructions`_ 549 ABS 1 legacy BPF packet access (absolute) `Legacy BPF Packet access instructions`_ 550 IND 2 legacy BPF packet access (indirect) `Legacy BPF Packet access instructions`_ 551 MEM 3 regular load and store operations `Regular load and store operations`_ 552 MEMSX 4 sign-extension load operations `Sign-extension load operations`_ 553 ATOMIC 6 atomic operations `Atomic operations`_ 554 ============= ===== ==================================== ============= 555 556**sz (size)** 557 The size modifier is one of: 558 559 ==== ===== ===================== 560 size value description 561 ==== ===== ===================== 562 W 0 word (4 bytes) 563 H 1 half word (2 bytes) 564 B 2 byte 565 DW 3 double word (8 bytes) 566 ==== ===== ===================== 567 568 Instructions using ``DW`` belong to the base64 conformance group. 569 570**class** 571 The instruction class (see `Instruction classes`_) 572 573Regular load and store operations 574--------------------------------- 575 576The ``MEM`` mode modifier is used to encode regular load and store 577instructions that transfer data between a register and memory. 578 579``{MEM, <size>, STX}`` means:: 580 581 *(size *) (dst + offset) = src 582 583``{MEM, <size>, ST}`` means:: 584 585 *(size *) (dst + offset) = imm 586 587``{MEM, <size>, LDX}`` means:: 588 589 dst = *(unsigned size *) (src + offset) 590 591Where '<size>' is one of: ``B``, ``H``, ``W``, or ``DW``, and 592'unsigned size' is one of: u8, u16, u32, or u64. 593 594Sign-extension load operations 595------------------------------ 596 597The ``MEMSX`` mode modifier is used to encode :term:`sign-extension<Sign Extend>` load 598instructions that transfer data between a register and memory. 599 600``{MEMSX, <size>, LDX}`` means:: 601 602 dst = *(signed size *) (src + offset) 603 604Where '<size>' is one of: ``B``, ``H``, or ``W``, and 605'signed size' is one of: s8, s16, or s32. 606 607Atomic operations 608----------------- 609 610Atomic operations are operations that operate on memory and can not be 611interrupted or corrupted by other access to the same memory region 612by other BPF programs or means outside of this specification. 613 614All atomic operations supported by BPF are encoded as store operations 615that use the ``ATOMIC`` mode modifier as follows: 616 617* ``{ATOMIC, W, STX}`` for 32-bit operations, which are 618 part of the "atomic32" conformance group. 619* ``{ATOMIC, DW, STX}`` for 64-bit operations, which are 620 part of the "atomic64" conformance group. 621* 8-bit and 16-bit wide atomic operations are not supported. 622 623The 'imm' field is used to encode the actual atomic operation. 624Simple atomic operation use a subset of the values defined to encode 625arithmetic operations in the 'imm' field to encode the atomic operation: 626 627======== ===== =========== 628imm value description 629======== ===== =========== 630ADD 0x00 atomic add 631OR 0x40 atomic or 632AND 0x50 atomic and 633XOR 0xa0 atomic xor 634======== ===== =========== 635 636 637``{ATOMIC, W, STX}`` with 'imm' = ADD means:: 638 639 *(u32 *)(dst + offset) += src 640 641``{ATOMIC, DW, STX}`` with 'imm' = ADD means:: 642 643 *(u64 *)(dst + offset) += src 644 645In addition to the simple atomic operations, there also is a modifier and 646two complex atomic operations: 647 648=========== ================ =========================== 649imm value description 650=========== ================ =========================== 651FETCH 0x01 modifier: return old value 652XCHG 0xe0 | FETCH atomic exchange 653CMPXCHG 0xf0 | FETCH atomic compare and exchange 654=========== ================ =========================== 655 656The ``FETCH`` modifier is optional for simple atomic operations, and 657always set for the complex atomic operations. If the ``FETCH`` flag 658is set, then the operation also overwrites ``src`` with the value that 659was in memory before it was modified. 660 661The ``XCHG`` operation atomically exchanges ``src`` with the value 662addressed by ``dst + offset``. 663 664The ``CMPXCHG`` operation atomically compares the value addressed by 665``dst + offset`` with ``R0``. If they match, the value addressed by 666``dst + offset`` is replaced with ``src``. In either case, the 667value that was at ``dst + offset`` before the operation is zero-extended 668and loaded back to ``R0``. 669 67064-bit immediate instructions 671----------------------------- 672 673Instructions with the ``IMM`` 'mode' modifier use the wide instruction 674encoding defined in `Instruction encoding`_, and use the 'src_reg' field of the 675basic instruction to hold an opcode subtype. 676 677The following table defines a set of ``{IMM, DW, LD}`` instructions 678with opcode subtypes in the 'src_reg' field, using new terms such as "map" 679defined further below: 680 681======= ========================================= =========== ============== 682src_reg pseudocode imm type dst type 683======= ========================================= =========== ============== 6840x0 dst = (next_imm << 32) | imm integer integer 6850x1 dst = map_by_fd(imm) map fd map 6860x2 dst = map_val(map_by_fd(imm)) + next_imm map fd data address 6870x3 dst = var_addr(imm) variable id data address 6880x4 dst = code_addr(imm) integer code address 6890x5 dst = map_by_idx(imm) map index map 6900x6 dst = map_val(map_by_idx(imm)) + next_imm map index data address 691======= ========================================= =========== ============== 692 693where 694 695* map_by_fd(imm) means to convert a 32-bit file descriptor into an address of a map (see `Maps`_) 696* map_by_idx(imm) means to convert a 32-bit index into an address of a map 697* map_val(map) gets the address of the first value in a given map 698* var_addr(imm) gets the address of a platform variable (see `Platform Variables`_) with a given id 699* code_addr(imm) gets the address of the instruction at a specified relative offset in number of (64-bit) instructions 700* the 'imm type' can be used by disassemblers for display 701* the 'dst type' can be used for verification and JIT compilation purposes 702 703Maps 704~~~~ 705 706Maps are shared memory regions accessible by BPF programs on some platforms. 707A map can have various semantics as defined in a separate document, and may or 708may not have a single contiguous memory region, but the 'map_val(map)' is 709currently only defined for maps that do have a single contiguous memory region. 710 711Each map can have a file descriptor (fd) if supported by the platform, where 712'map_by_fd(imm)' means to get the map with the specified file descriptor. Each 713BPF program can also be defined to use a set of maps associated with the 714program at load time, and 'map_by_idx(imm)' means to get the map with the given 715index in the set associated with the BPF program containing the instruction. 716 717Platform Variables 718~~~~~~~~~~~~~~~~~~ 719 720Platform variables are memory regions, identified by integer ids, exposed by 721the runtime and accessible by BPF programs on some platforms. The 722'var_addr(imm)' operation means to get the address of the memory region 723identified by the given id. 724 725Legacy BPF Packet access instructions 726------------------------------------- 727 728BPF previously introduced special instructions for access to packet data that were 729carried over from classic BPF. These instructions used an instruction 730class of ``LD``, a size modifier of ``W``, ``H``, or ``B``, and a 731mode modifier of ``ABS`` or ``IND``. The 'dst_reg' and 'offset' fields were 732set to zero, and 'src_reg' was set to zero for ``ABS``. However, these 733instructions are deprecated and SHOULD no longer be used. All legacy packet 734access instructions belong to the "packet" conformance group. 735