1.. contents:: 2.. sectnum:: 3 4====================================== 5BPF Instruction Set Architecture (ISA) 6====================================== 7 8eBPF (which is no longer an acronym for anything), also commonly 9referred to as BPF, is a technology with origins in the Linux kernel 10that can run untrusted programs in a privileged context such as an 11operating system kernel. This document specifies the BPF instruction 12set architecture (ISA). 13 14Documentation conventions 15========================= 16 17For brevity and consistency, this document refers to families 18of types using a shorthand syntax and refers to several expository, 19mnemonic functions when describing the semantics of instructions. 20The range of valid values for those types and the semantics of those 21functions are defined in the following subsections. 22 23Types 24----- 25This document refers to integer types with the notation `SN` to specify 26a type's signedness (`S`) and bit width (`N`), respectively. 27 28.. table:: Meaning of signedness notation. 29 30 ==== ========= 31 S Meaning 32 ==== ========= 33 u unsigned 34 s signed 35 ==== ========= 36 37.. table:: Meaning of bit-width notation. 38 39 ===== ========= 40 N Bit width 41 ===== ========= 42 8 8 bits 43 16 16 bits 44 32 32 bits 45 64 64 bits 46 128 128 bits 47 ===== ========= 48 49For example, `u32` is a type whose valid values are all the 32-bit unsigned 50numbers and `s16` is a type whose valid values are all the 16-bit signed 51numbers. 52 53Functions 54--------- 55* htobe16: Takes an unsigned 16-bit number in host-endian format and 56 returns the equivalent number as an unsigned 16-bit number in big-endian 57 format. 58* htobe32: Takes an unsigned 32-bit number in host-endian format and 59 returns the equivalent number as an unsigned 32-bit number in big-endian 60 format. 61* htobe64: Takes an unsigned 64-bit number in host-endian format and 62 returns the equivalent number as an unsigned 64-bit number in big-endian 63 format. 64* htole16: Takes an unsigned 16-bit number in host-endian format and 65 returns the equivalent number as an unsigned 16-bit number in little-endian 66 format. 67* htole32: Takes an unsigned 32-bit number in host-endian format and 68 returns the equivalent number as an unsigned 32-bit number in little-endian 69 format. 70* htole64: Takes an unsigned 64-bit number in host-endian format and 71 returns the equivalent number as an unsigned 64-bit number in little-endian 72 format. 73* bswap16: Takes an unsigned 16-bit number in either big- or little-endian 74 format and returns the equivalent number with the same bit width but 75 opposite endianness. 76* bswap32: Takes an unsigned 32-bit number in either big- or little-endian 77 format and returns the equivalent number with the same bit width but 78 opposite endianness. 79* bswap64: Takes an unsigned 64-bit number in either big- or little-endian 80 format and returns the equivalent number with the same bit width but 81 opposite endianness. 82 83 84Definitions 85----------- 86 87.. glossary:: 88 89 Sign Extend 90 To `sign extend an` ``X`` `-bit number, A, to a` ``Y`` `-bit number, B ,` means to 91 92 #. Copy all ``X`` bits from `A` to the lower ``X`` bits of `B`. 93 #. Set the value of the remaining ``Y`` - ``X`` bits of `B` to the value of 94 the most-significant bit of `A`. 95 96.. admonition:: Example 97 98 Sign extend an 8-bit number ``A`` to a 16-bit number ``B`` on a big-endian platform: 99 :: 100 101 A: 10000110 102 B: 11111111 10000110 103 104Conformance groups 105------------------ 106 107An implementation does not need to support all instructions specified in this 108document (e.g., deprecated instructions). Instead, a number of conformance 109groups are specified. An implementation must support the base32 conformance 110group and may support additional conformance groups, where supporting a 111conformance group means it must support all instructions in that conformance 112group. 113 114The use of named conformance groups enables interoperability between a runtime 115that executes instructions, and tools such as compilers that generate 116instructions for the runtime. Thus, capability discovery in terms of 117conformance groups might be done manually by users or automatically by tools. 118 119Each conformance group has a short ASCII label (e.g., "base32") that 120corresponds to a set of instructions that are mandatory. That is, each 121instruction has one or more conformance groups of which it is a member. 122 123This document defines the following conformance groups: 124 125* base32: includes all instructions defined in this 126 specification unless otherwise noted. 127* base64: includes base32, plus instructions explicitly noted 128 as being in the base64 conformance group. 129* atomic32: includes 32-bit atomic operation instructions (see `Atomic operations`_). 130* atomic64: includes atomic32, plus 64-bit atomic operation instructions. 131* divmul32: includes 32-bit division, multiplication, and modulo instructions. 132* divmul64: includes divmul32, plus 64-bit division, multiplication, 133 and modulo instructions. 134* packet: deprecated packet access instructions. 135 136Instruction encoding 137==================== 138 139BPF has two instruction encodings: 140 141* the basic instruction encoding, which uses 64 bits to encode an instruction 142* the wide instruction encoding, which appends a second 64 bits 143 after the basic instruction for a total of 128 bits. 144 145Basic instruction encoding 146-------------------------- 147 148A basic instruction is encoded as follows:: 149 150 +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 151 | opcode | regs | offset | 152 +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 153 | imm | 154 +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 155 156**opcode** 157 operation to perform, encoded as follows:: 158 159 +-+-+-+-+-+-+-+-+ 160 |specific |class| 161 +-+-+-+-+-+-+-+-+ 162 163 **specific** 164 The format of these bits varies by instruction class 165 166 **class** 167 The instruction class (see `Instruction classes`_) 168 169**regs** 170 The source and destination register numbers, encoded as follows 171 on a little-endian host:: 172 173 +-+-+-+-+-+-+-+-+ 174 |src_reg|dst_reg| 175 +-+-+-+-+-+-+-+-+ 176 177 and as follows on a big-endian host:: 178 179 +-+-+-+-+-+-+-+-+ 180 |dst_reg|src_reg| 181 +-+-+-+-+-+-+-+-+ 182 183 **src_reg** 184 the source register number (0-10), except where otherwise specified 185 (`64-bit immediate instructions`_ reuse this field for other purposes) 186 187 **dst_reg** 188 destination register number (0-10), unless otherwise specified 189 (future instructions might reuse this field for other purposes) 190 191**offset** 192 signed integer offset used with pointer arithmetic, except where 193 otherwise specified (some arithmetic instructions reuse this field 194 for other purposes) 195 196**imm** 197 signed integer immediate value 198 199Note that the contents of multi-byte fields ('offset' and 'imm') are 200stored using big-endian byte ordering on big-endian hosts and 201little-endian byte ordering on little-endian hosts. 202 203For example:: 204 205 opcode offset imm assembly 206 src_reg dst_reg 207 07 0 1 00 00 44 33 22 11 r1 += 0x11223344 // little 208 dst_reg src_reg 209 07 1 0 00 00 11 22 33 44 r1 += 0x11223344 // big 210 211Note that most instructions do not use all of the fields. 212Unused fields shall be cleared to zero. 213 214Wide instruction encoding 215-------------------------- 216 217Some instructions are defined to use the wide instruction encoding, 218which uses two 32-bit immediate values. The 64 bits following 219the basic instruction format contain a pseudo instruction 220with 'opcode', 'dst_reg', 'src_reg', and 'offset' all set to zero. 221 222This is depicted in the following figure:: 223 224 +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 225 | opcode | regs | offset | 226 +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 227 | imm | 228 +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 229 | reserved | 230 +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 231 | next_imm | 232 +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 233 234**opcode** 235 operation to perform, encoded as explained above 236 237**regs** 238 The source and destination register numbers (unless otherwise 239 specified), encoded as explained above 240 241**offset** 242 signed integer offset used with pointer arithmetic, unless 243 otherwise specified 244 245**imm** 246 signed integer immediate value 247 248**reserved** 249 unused, set to zero 250 251**next_imm** 252 second signed integer immediate value 253 254Instruction classes 255------------------- 256 257The three least significant bits of the 'opcode' field store the instruction class: 258 259===== ===== =============================== =================================== 260class value description reference 261===== ===== =============================== =================================== 262LD 0x0 non-standard load operations `Load and store instructions`_ 263LDX 0x1 load into register operations `Load and store instructions`_ 264ST 0x2 store from immediate operations `Load and store instructions`_ 265STX 0x3 store from register operations `Load and store instructions`_ 266ALU 0x4 32-bit arithmetic operations `Arithmetic and jump instructions`_ 267JMP 0x5 64-bit jump operations `Arithmetic and jump instructions`_ 268JMP32 0x6 32-bit jump operations `Arithmetic and jump instructions`_ 269ALU64 0x7 64-bit arithmetic operations `Arithmetic and jump instructions`_ 270===== ===== =============================== =================================== 271 272Arithmetic and jump instructions 273================================ 274 275For arithmetic and jump instructions (``ALU``, ``ALU64``, ``JMP`` and 276``JMP32``), the 8-bit 'opcode' field is divided into three parts:: 277 278 +-+-+-+-+-+-+-+-+ 279 | code |s|class| 280 +-+-+-+-+-+-+-+-+ 281 282**code** 283 the operation code, whose meaning varies by instruction class 284 285**s (source)** 286 the source operand location, which unless otherwise specified is one of: 287 288 ====== ===== ============================================== 289 source value description 290 ====== ===== ============================================== 291 K 0 use 32-bit 'imm' value as source operand 292 X 1 use 'src_reg' register value as source operand 293 ====== ===== ============================================== 294 295**instruction class** 296 the instruction class (see `Instruction classes`_) 297 298Arithmetic instructions 299----------------------- 300 301``ALU`` uses 32-bit wide operands while ``ALU64`` uses 64-bit wide operands for 302otherwise identical operations. ``ALU64`` instructions belong to the 303base64 conformance group unless noted otherwise. 304The 'code' field encodes the operation as below, where 'src' and 'dst' refer 305to the values of the source and destination registers, respectively. 306 307===== ===== ======= ========================================================== 308name code offset description 309===== ===== ======= ========================================================== 310ADD 0x0 0 dst += src 311SUB 0x1 0 dst -= src 312MUL 0x2 0 dst \*= src 313DIV 0x3 0 dst = (src != 0) ? (dst / src) : 0 314SDIV 0x3 1 dst = (src != 0) ? (dst s/ src) : 0 315OR 0x4 0 dst \|= src 316AND 0x5 0 dst &= src 317LSH 0x6 0 dst <<= (src & mask) 318RSH 0x7 0 dst >>= (src & mask) 319NEG 0x8 0 dst = -dst 320MOD 0x9 0 dst = (src != 0) ? (dst % src) : dst 321SMOD 0x9 1 dst = (src != 0) ? (dst s% src) : dst 322XOR 0xa 0 dst ^= src 323MOV 0xb 0 dst = src 324MOVSX 0xb 8/16/32 dst = (s8,s16,s32)src 325ARSH 0xc 0 :term:`sign extending<Sign Extend>` dst >>= (src & mask) 326END 0xd 0 byte swap operations (see `Byte swap instructions`_ below) 327===== ===== ======= ========================================================== 328 329Underflow and overflow are allowed during arithmetic operations, meaning 330the 64-bit or 32-bit value will wrap. If BPF program execution would 331result in division by zero, the destination register is instead set to zero. 332If execution would result in modulo by zero, for ``ALU64`` the value of 333the destination register is unchanged whereas for ``ALU`` the upper 33432 bits of the destination register are zeroed. 335 336``{ADD, X, ALU}``, where 'code' = ``ADD``, 'source' = ``X``, and 'class' = ``ALU``, means:: 337 338 dst = (u32) ((u32) dst + (u32) src) 339 340where '(u32)' indicates that the upper 32 bits are zeroed. 341 342``{ADD, X, ALU64}`` means:: 343 344 dst = dst + src 345 346``{XOR, K, ALU}`` means:: 347 348 dst = (u32) dst ^ (u32) imm 349 350``{XOR, K, ALU64}`` means:: 351 352 dst = dst ^ imm 353 354Note that most arithmetic instructions have 'offset' set to 0. Only three instructions 355(``SDIV``, ``SMOD``, ``MOVSX``) have a non-zero 'offset'. 356 357Division, multiplication, and modulo operations for ``ALU`` are part 358of the "divmul32" conformance group, and division, multiplication, and 359modulo operations for ``ALU64`` are part of the "divmul64" conformance 360group. 361The division and modulo operations support both unsigned and signed flavors. 362 363For unsigned operations (``DIV`` and ``MOD``), for ``ALU``, 364'imm' is interpreted as a 32-bit unsigned value. For ``ALU64``, 365'imm' is first :term:`sign extended<Sign Extend>` from 32 to 64 bits, and then 366interpreted as a 64-bit unsigned value. 367 368For signed operations (``SDIV`` and ``SMOD``), for ``ALU``, 369'imm' is interpreted as a 32-bit signed value. For ``ALU64``, 'imm' 370is first :term:`sign extended<Sign Extend>` from 32 to 64 bits, and then 371interpreted as a 64-bit signed value. 372 373Note that there are varying definitions of the signed modulo operation 374when the dividend or divisor are negative, where implementations often 375vary by language such that Python, Ruby, etc. differ from C, Go, Java, 376etc. This specification requires that signed modulo use truncated division 377(where -13 % 3 == -1) as implemented in C, Go, etc.:: 378 379 a % n = a - n * trunc(a / n) 380 381The ``MOVSX`` instruction does a move operation with sign extension. 382``{MOVSX, X, ALU}`` :term:`sign extends<Sign Extend>` 8-bit and 16-bit operands into 38332-bit operands, and zeroes the remaining upper 32 bits. 384``{MOVSX, X, ALU64}`` :term:`sign extends<Sign Extend>` 8-bit, 16-bit, and 32-bit 385operands into 64-bit operands. Unlike other arithmetic instructions, 386``MOVSX`` is only defined for register source operands (``X``). 387 388The ``NEG`` instruction is only defined when the source bit is clear 389(``K``). 390 391Shift operations use a mask of 0x3F (63) for 64-bit operations and 0x1F (31) 392for 32-bit operations. 393 394Byte swap instructions 395---------------------- 396 397The byte swap instructions use instruction classes of ``ALU`` and ``ALU64`` 398and a 4-bit 'code' field of ``END``. 399 400The byte swap instructions operate on the destination register 401only and do not use a separate source register or immediate value. 402 403For ``ALU``, the 1-bit source operand field in the opcode is used to 404select what byte order the operation converts from or to. For 405``ALU64``, the 1-bit source operand field in the opcode is reserved 406and must be set to 0. 407 408===== ======== ===== ================================================= 409class source value description 410===== ======== ===== ================================================= 411ALU TO_LE 0 convert between host byte order and little endian 412ALU TO_BE 1 convert between host byte order and big endian 413ALU64 Reserved 0 do byte swap unconditionally 414===== ======== ===== ================================================= 415 416The 'imm' field encodes the width of the swap operations. The following widths 417are supported: 16, 32 and 64. Width 64 operations belong to the base64 418conformance group and other swap operations belong to the base32 419conformance group. 420 421Examples: 422 423``{END, TO_LE, ALU}`` with 'imm' = 16/32/64 means:: 424 425 dst = htole16(dst) 426 dst = htole32(dst) 427 dst = htole64(dst) 428 429``{END, TO_BE, ALU}`` with 'imm' = 16/32/64 means:: 430 431 dst = htobe16(dst) 432 dst = htobe32(dst) 433 dst = htobe64(dst) 434 435``{END, TO_LE, ALU64}`` with 'imm' = 16/32/64 means:: 436 437 dst = bswap16(dst) 438 dst = bswap32(dst) 439 dst = bswap64(dst) 440 441Jump instructions 442----------------- 443 444``JMP32`` uses 32-bit wide operands and indicates the base32 445conformance group, while ``JMP`` uses 64-bit wide operands for 446otherwise identical operations, and indicates the base64 conformance 447group unless otherwise specified. 448The 'code' field encodes the operation as below: 449 450======== ===== ======= ================================= =================================================== 451code value src_reg description notes 452======== ===== ======= ================================= =================================================== 453JA 0x0 0x0 PC += offset {JA, K, JMP} only 454JA 0x0 0x0 PC += imm {JA, K, JMP32} only 455JEQ 0x1 any PC += offset if dst == src 456JGT 0x2 any PC += offset if dst > src unsigned 457JGE 0x3 any PC += offset if dst >= src unsigned 458JSET 0x4 any PC += offset if dst & src 459JNE 0x5 any PC += offset if dst != src 460JSGT 0x6 any PC += offset if dst > src signed 461JSGE 0x7 any PC += offset if dst >= src signed 462CALL 0x8 0x0 call helper function by static ID {CALL, K, JMP} only, see `Helper functions`_ 463CALL 0x8 0x1 call PC += imm {CALL, K, JMP} only, see `Program-local functions`_ 464CALL 0x8 0x2 call helper function by BTF ID {CALL, K, JMP} only, see `Helper functions`_ 465EXIT 0x9 0x0 return {CALL, K, JMP} only 466JLT 0xa any PC += offset if dst < src unsigned 467JLE 0xb any PC += offset if dst <= src unsigned 468JSLT 0xc any PC += offset if dst < src signed 469JSLE 0xd any PC += offset if dst <= src signed 470======== ===== ======= ================================= =================================================== 471 472where 'PC' denotes the program counter, and the offset to increment by 473is in units of 64-bit instructions relative to the instruction following 474the jump instruction. Thus 'PC += 1' skips execution of the next 475instruction if it's a basic instruction or results in undefined behavior 476if the next instruction is a 128-bit wide instruction. 477 478The BPF program needs to store the return value into register R0 before doing an 479``EXIT``. 480 481Example: 482 483``{JSGE, X, JMP32}`` means:: 484 485 if (s32)dst s>= (s32)src goto +offset 486 487where 's>=' indicates a signed '>=' comparison. 488 489``{JA, K, JMP32}`` means:: 490 491 gotol +imm 492 493where 'imm' means the branch offset comes from the 'imm' field. 494 495Note that there are two flavors of ``JA`` instructions. The 496``JMP`` class permits a 16-bit jump offset specified by the 'offset' 497field, whereas the ``JMP32`` class permits a 32-bit jump offset 498specified by the 'imm' field. A > 16-bit conditional jump may be 499converted to a < 16-bit conditional jump plus a 32-bit unconditional 500jump. 501 502All ``CALL`` and ``JA`` instructions belong to the 503base32 conformance group. 504 505Helper functions 506~~~~~~~~~~~~~~~~ 507 508Helper functions are a concept whereby BPF programs can call into a 509set of function calls exposed by the underlying platform. 510 511Historically, each helper function was identified by a static ID 512encoded in the 'imm' field. The available helper functions may differ 513for each program type, but static IDs are unique across all program types. 514 515Platforms that support the BPF Type Format (BTF) support identifying 516a helper function by a BTF ID encoded in the 'imm' field, where the BTF ID 517identifies the helper name and type. 518 519Program-local functions 520~~~~~~~~~~~~~~~~~~~~~~~ 521Program-local functions are functions exposed by the same BPF program as the 522caller, and are referenced by offset from the call instruction, similar to 523``JA``. The offset is encoded in the 'imm' field of the call instruction. 524An ``EXIT`` within the program-local function will return to the caller. 525 526Load and store instructions 527=========================== 528 529For load and store instructions (``LD``, ``LDX``, ``ST``, and ``STX``), the 5308-bit 'opcode' field is divided as follows:: 531 532 +-+-+-+-+-+-+-+-+ 533 |mode |sz |class| 534 +-+-+-+-+-+-+-+-+ 535 536**mode** 537 The mode modifier is one of: 538 539 ============= ===== ==================================== ============= 540 mode modifier value description reference 541 ============= ===== ==================================== ============= 542 IMM 0 64-bit immediate instructions `64-bit immediate instructions`_ 543 ABS 1 legacy BPF packet access (absolute) `Legacy BPF Packet access instructions`_ 544 IND 2 legacy BPF packet access (indirect) `Legacy BPF Packet access instructions`_ 545 MEM 3 regular load and store operations `Regular load and store operations`_ 546 MEMSX 4 sign-extension load operations `Sign-extension load operations`_ 547 ATOMIC 6 atomic operations `Atomic operations`_ 548 ============= ===== ==================================== ============= 549 550**sz (size)** 551 The size modifier is one of: 552 553 ==== ===== ===================== 554 size value description 555 ==== ===== ===================== 556 W 0 word (4 bytes) 557 H 1 half word (2 bytes) 558 B 2 byte 559 DW 3 double word (8 bytes) 560 ==== ===== ===================== 561 562 Instructions using ``DW`` belong to the base64 conformance group. 563 564**class** 565 The instruction class (see `Instruction classes`_) 566 567Regular load and store operations 568--------------------------------- 569 570The ``MEM`` mode modifier is used to encode regular load and store 571instructions that transfer data between a register and memory. 572 573``{MEM, <size>, STX}`` means:: 574 575 *(size *) (dst + offset) = src 576 577``{MEM, <size>, ST}`` means:: 578 579 *(size *) (dst + offset) = imm 580 581``{MEM, <size>, LDX}`` means:: 582 583 dst = *(unsigned size *) (src + offset) 584 585Where '<size>' is one of: ``B``, ``H``, ``W``, or ``DW``, and 586'unsigned size' is one of: u8, u16, u32, or u64. 587 588Sign-extension load operations 589------------------------------ 590 591The ``MEMSX`` mode modifier is used to encode :term:`sign-extension<Sign Extend>` load 592instructions that transfer data between a register and memory. 593 594``{MEMSX, <size>, LDX}`` means:: 595 596 dst = *(signed size *) (src + offset) 597 598Where '<size>' is one of: ``B``, ``H``, or ``W``, and 599'signed size' is one of: s8, s16, or s32. 600 601Atomic operations 602----------------- 603 604Atomic operations are operations that operate on memory and can not be 605interrupted or corrupted by other access to the same memory region 606by other BPF programs or means outside of this specification. 607 608All atomic operations supported by BPF are encoded as store operations 609that use the ``ATOMIC`` mode modifier as follows: 610 611* ``{ATOMIC, W, STX}`` for 32-bit operations, which are 612 part of the "atomic32" conformance group. 613* ``{ATOMIC, DW, STX}`` for 64-bit operations, which are 614 part of the "atomic64" conformance group. 615* 8-bit and 16-bit wide atomic operations are not supported. 616 617The 'imm' field is used to encode the actual atomic operation. 618Simple atomic operation use a subset of the values defined to encode 619arithmetic operations in the 'imm' field to encode the atomic operation: 620 621======== ===== =========== 622imm value description 623======== ===== =========== 624ADD 0x00 atomic add 625OR 0x40 atomic or 626AND 0x50 atomic and 627XOR 0xa0 atomic xor 628======== ===== =========== 629 630 631``{ATOMIC, W, STX}`` with 'imm' = ADD means:: 632 633 *(u32 *)(dst + offset) += src 634 635``{ATOMIC, DW, STX}`` with 'imm' = ADD means:: 636 637 *(u64 *)(dst + offset) += src 638 639In addition to the simple atomic operations, there also is a modifier and 640two complex atomic operations: 641 642=========== ================ =========================== 643imm value description 644=========== ================ =========================== 645FETCH 0x01 modifier: return old value 646XCHG 0xe0 | FETCH atomic exchange 647CMPXCHG 0xf0 | FETCH atomic compare and exchange 648=========== ================ =========================== 649 650The ``FETCH`` modifier is optional for simple atomic operations, and 651always set for the complex atomic operations. If the ``FETCH`` flag 652is set, then the operation also overwrites ``src`` with the value that 653was in memory before it was modified. 654 655The ``XCHG`` operation atomically exchanges ``src`` with the value 656addressed by ``dst + offset``. 657 658The ``CMPXCHG`` operation atomically compares the value addressed by 659``dst + offset`` with ``R0``. If they match, the value addressed by 660``dst + offset`` is replaced with ``src``. In either case, the 661value that was at ``dst + offset`` before the operation is zero-extended 662and loaded back to ``R0``. 663 66464-bit immediate instructions 665----------------------------- 666 667Instructions with the ``IMM`` 'mode' modifier use the wide instruction 668encoding defined in `Instruction encoding`_, and use the 'src_reg' field of the 669basic instruction to hold an opcode subtype. 670 671The following table defines a set of ``{IMM, DW, LD}`` instructions 672with opcode subtypes in the 'src_reg' field, using new terms such as "map" 673defined further below: 674 675======= ========================================= =========== ============== 676src_reg pseudocode imm type dst type 677======= ========================================= =========== ============== 6780x0 dst = (next_imm << 32) | imm integer integer 6790x1 dst = map_by_fd(imm) map fd map 6800x2 dst = map_val(map_by_fd(imm)) + next_imm map fd data address 6810x3 dst = var_addr(imm) variable id data address 6820x4 dst = code_addr(imm) integer code address 6830x5 dst = map_by_idx(imm) map index map 6840x6 dst = map_val(map_by_idx(imm)) + next_imm map index data address 685======= ========================================= =========== ============== 686 687where 688 689* map_by_fd(imm) means to convert a 32-bit file descriptor into an address of a map (see `Maps`_) 690* map_by_idx(imm) means to convert a 32-bit index into an address of a map 691* map_val(map) gets the address of the first value in a given map 692* var_addr(imm) gets the address of a platform variable (see `Platform Variables`_) with a given id 693* code_addr(imm) gets the address of the instruction at a specified relative offset in number of (64-bit) instructions 694* the 'imm type' can be used by disassemblers for display 695* the 'dst type' can be used for verification and JIT compilation purposes 696 697Maps 698~~~~ 699 700Maps are shared memory regions accessible by BPF programs on some platforms. 701A map can have various semantics as defined in a separate document, and may or 702may not have a single contiguous memory region, but the 'map_val(map)' is 703currently only defined for maps that do have a single contiguous memory region. 704 705Each map can have a file descriptor (fd) if supported by the platform, where 706'map_by_fd(imm)' means to get the map with the specified file descriptor. Each 707BPF program can also be defined to use a set of maps associated with the 708program at load time, and 'map_by_idx(imm)' means to get the map with the given 709index in the set associated with the BPF program containing the instruction. 710 711Platform Variables 712~~~~~~~~~~~~~~~~~~ 713 714Platform variables are memory regions, identified by integer ids, exposed by 715the runtime and accessible by BPF programs on some platforms. The 716'var_addr(imm)' operation means to get the address of the memory region 717identified by the given id. 718 719Legacy BPF Packet access instructions 720------------------------------------- 721 722BPF previously introduced special instructions for access to packet data that were 723carried over from classic BPF. These instructions used an instruction 724class of ``LD``, a size modifier of ``W``, ``H``, or ``B``, and a 725mode modifier of ``ABS`` or ``IND``. The 'dst_reg' and 'offset' fields were 726set to zero, and 'src_reg' was set to zero for ``ABS``. However, these 727instructions are deprecated and should no longer be used. All legacy packet 728access instructions belong to the "packet" conformance group. 729