187670c57SJonathan Corbet=========================================== 287670c57SJonathan CorbetAtomic Operation Control (ATOMCTL) Register 387670c57SJonathan Corbet=========================================== 487670c57SJonathan Corbet 587670c57SJonathan CorbetWe Have Atomic Operation Control (ATOMCTL) Register. 687670c57SJonathan CorbetThis register determines the effect of using a S32C1I instruction 787670c57SJonathan Corbetwith various combinations of: 887670c57SJonathan Corbet 987670c57SJonathan Corbet 1. With and without an Coherent Cache Controller which 1087670c57SJonathan Corbet can do Atomic Transactions to the memory internally. 1187670c57SJonathan Corbet 1287670c57SJonathan Corbet 2. With and without An Intelligent Memory Controller which 1387670c57SJonathan Corbet can do Atomic Transactions itself. 1487670c57SJonathan Corbet 1587670c57SJonathan CorbetThe Core comes up with a default value of for the three types of cache ops:: 1687670c57SJonathan Corbet 1787670c57SJonathan Corbet 0x28: (WB: Internal, WT: Internal, BY:Exception) 1887670c57SJonathan Corbet 1987670c57SJonathan CorbetOn the FPGA Cards we typically simulate an Intelligent Memory controller 2087670c57SJonathan Corbetwhich can implement RCW transactions. For FPGA cards with an External 2187670c57SJonathan CorbetMemory controller we let it to the atomic operations internally while 2287670c57SJonathan Corbetdoing a Cached (WB) transaction and use the Memory RCW for un-cached 2387670c57SJonathan Corbetoperations. 2487670c57SJonathan Corbet 2587670c57SJonathan CorbetFor systems without an coherent cache controller, non-MX, we always 26*d56b699dSBjorn Helgaasuse the memory controllers RCW, though non-MX controllers likely 2787670c57SJonathan Corbetsupport the Internal Operation. 2887670c57SJonathan Corbet 2987670c57SJonathan CorbetCUSTOMER-WARNING: 3087670c57SJonathan Corbet Virtually all customers buy their memory controllers from vendors that 3187670c57SJonathan Corbet don't support atomic RCW memory transactions and will likely want to 3287670c57SJonathan Corbet configure this register to not use RCW. 3387670c57SJonathan Corbet 3487670c57SJonathan CorbetDevelopers might find using RCW in Bypass mode convenient when testing 3587670c57SJonathan Corbetwith the cache being bypassed; for example studying cache alias problems. 3687670c57SJonathan Corbet 3787670c57SJonathan CorbetSee Section 4.3.12.4 of ISA; Bits:: 3887670c57SJonathan Corbet 3987670c57SJonathan Corbet WB WT BY 4087670c57SJonathan Corbet 5 4 | 3 2 | 1 0 4187670c57SJonathan Corbet 4287670c57SJonathan Corbet========= ================== ================== =============== 4387670c57SJonathan Corbet 2 Bit 4487670c57SJonathan Corbet Field 4587670c57SJonathan Corbet Values WB - Write Back WT - Write Thru BY - Bypass 4687670c57SJonathan Corbet========= ================== ================== =============== 4787670c57SJonathan Corbet 0 Exception Exception Exception 4887670c57SJonathan Corbet 1 RCW Transaction RCW Transaction RCW Transaction 4987670c57SJonathan Corbet 2 Internal Operation Internal Operation Reserved 5087670c57SJonathan Corbet 3 Reserved Reserved Reserved 5187670c57SJonathan Corbet========= ================== ================== =============== 52