1*87670c57SJonathan Corbet=========================================== 2*87670c57SJonathan CorbetAtomic Operation Control (ATOMCTL) Register 3*87670c57SJonathan Corbet=========================================== 4*87670c57SJonathan Corbet 5*87670c57SJonathan CorbetWe Have Atomic Operation Control (ATOMCTL) Register. 6*87670c57SJonathan CorbetThis register determines the effect of using a S32C1I instruction 7*87670c57SJonathan Corbetwith various combinations of: 8*87670c57SJonathan Corbet 9*87670c57SJonathan Corbet 1. With and without an Coherent Cache Controller which 10*87670c57SJonathan Corbet can do Atomic Transactions to the memory internally. 11*87670c57SJonathan Corbet 12*87670c57SJonathan Corbet 2. With and without An Intelligent Memory Controller which 13*87670c57SJonathan Corbet can do Atomic Transactions itself. 14*87670c57SJonathan Corbet 15*87670c57SJonathan CorbetThe Core comes up with a default value of for the three types of cache ops:: 16*87670c57SJonathan Corbet 17*87670c57SJonathan Corbet 0x28: (WB: Internal, WT: Internal, BY:Exception) 18*87670c57SJonathan Corbet 19*87670c57SJonathan CorbetOn the FPGA Cards we typically simulate an Intelligent Memory controller 20*87670c57SJonathan Corbetwhich can implement RCW transactions. For FPGA cards with an External 21*87670c57SJonathan CorbetMemory controller we let it to the atomic operations internally while 22*87670c57SJonathan Corbetdoing a Cached (WB) transaction and use the Memory RCW for un-cached 23*87670c57SJonathan Corbetoperations. 24*87670c57SJonathan Corbet 25*87670c57SJonathan CorbetFor systems without an coherent cache controller, non-MX, we always 26*87670c57SJonathan Corbetuse the memory controllers RCW, thought non-MX controlers likely 27*87670c57SJonathan Corbetsupport the Internal Operation. 28*87670c57SJonathan Corbet 29*87670c57SJonathan CorbetCUSTOMER-WARNING: 30*87670c57SJonathan Corbet Virtually all customers buy their memory controllers from vendors that 31*87670c57SJonathan Corbet don't support atomic RCW memory transactions and will likely want to 32*87670c57SJonathan Corbet configure this register to not use RCW. 33*87670c57SJonathan Corbet 34*87670c57SJonathan CorbetDevelopers might find using RCW in Bypass mode convenient when testing 35*87670c57SJonathan Corbetwith the cache being bypassed; for example studying cache alias problems. 36*87670c57SJonathan Corbet 37*87670c57SJonathan CorbetSee Section 4.3.12.4 of ISA; Bits:: 38*87670c57SJonathan Corbet 39*87670c57SJonathan Corbet WB WT BY 40*87670c57SJonathan Corbet 5 4 | 3 2 | 1 0 41*87670c57SJonathan Corbet 42*87670c57SJonathan Corbet========= ================== ================== =============== 43*87670c57SJonathan Corbet 2 Bit 44*87670c57SJonathan Corbet Field 45*87670c57SJonathan Corbet Values WB - Write Back WT - Write Thru BY - Bypass 46*87670c57SJonathan Corbet========= ================== ================== =============== 47*87670c57SJonathan Corbet 0 Exception Exception Exception 48*87670c57SJonathan Corbet 1 RCW Transaction RCW Transaction RCW Transaction 49*87670c57SJonathan Corbet 2 Internal Operation Internal Operation Reserved 50*87670c57SJonathan Corbet 3 Reserved Reserved Reserved 51*87670c57SJonathan Corbet========= ================== ================== =============== 52