1.. SPDX-License-Identifier: GPL-2.0 2 3RISC-V Linux User ABI 4===================== 5 6ISA string ordering in /proc/cpuinfo 7------------------------------------ 8 9The canonical order of ISA extension names in the ISA string is defined in 10Chapter 27 of the RISC-V Instruction Set Manual Volume I Unprivileged ISA 11(Document Version 20191213). 12 13The specification uses vague wording, such as should, when it comes to ordering, 14so for our purposes the following rules apply: 15 16#. Single-letter extensions come first, in canonical order. 17 The canonical order is "IMAFDQLCBKJTPVH". 18 19#. All multi-letter extensions will be separated from other extensions by an 20 underscore. 21 22#. Additional standard extensions (starting with 'Z') will be sorted after 23 single-letter extensions and before any higher-privileged extensions. 24 25#. For additional standard extensions, the first letter following the 'Z' 26 conventionally indicates the most closely related alphabetical 27 extension category. If multiple 'Z' extensions are named, they will be 28 ordered first by category, in canonical order, as listed above, then 29 alphabetically within a category. 30 31#. Standard supervisor-level extensions (starting with 'S') will be listed 32 after standard unprivileged extensions. If multiple supervisor-level 33 extensions are listed, they will be ordered alphabetically. 34 35#. Standard machine-level extensions (starting with 'Zxm') will be listed 36 after any lower-privileged, standard extensions. If multiple machine-level 37 extensions are listed, they will be ordered alphabetically. 38 39#. Non-standard extensions (starting with 'X') will be listed after all standard 40 extensions. If multiple non-standard extensions are listed, they will be 41 ordered alphabetically. 42 43An example string following the order is:: 44 45 rv64imadc_zifoo_zigoo_zafoo_sbar_scar_zxmbaz_xqux_xrux 46 47"isa" and "hart isa" lines in /proc/cpuinfo 48------------------------------------------- 49 50The "isa" line in /proc/cpuinfo describes the lowest common denominator of 51RISC-V ISA extensions recognized by the kernel and implemented on all harts. The 52"hart isa" line, in contrast, describes the set of extensions recognized by the 53kernel on the particular hart being described, even if those extensions may not 54be present on all harts in the system. 55 56In both lines, the presence of an extension guarantees only that the hardware 57has the described capability. Additional kernel support or policy changes may be 58required before an extension's capability is fully usable by userspace programs. 59Similarly, for S-mode extensions, presence in one of these lines does not 60guarantee that the kernel is taking advantage of the extension, or that the 61feature will be visible in guest VMs managed by this kernel. 62 63Inversely, the absence of an extension in these lines does not necessarily mean 64the hardware does not support that feature. The running kernel may not recognize 65the extension, or may have deliberately removed it from the listing. 66 67Misaligned accesses 68------------------- 69 70Misaligned scalar accesses are supported in userspace, but they may perform 71poorly. Misaligned vector accesses are only supported if the Zicclsm extension 72is supported. 73 74Pointer masking 75--------------- 76 77Support for pointer masking in userspace (the Supm extension) is provided via 78the ``PR_SET_TAGGED_ADDR_CTRL`` and ``PR_GET_TAGGED_ADDR_CTRL`` ``prctl()`` 79operations. Pointer masking is disabled by default. To enable it, userspace 80must call ``PR_SET_TAGGED_ADDR_CTRL`` with the ``PR_PMLEN`` field set to the 81number of mask/tag bits needed by the application. ``PR_PMLEN`` is interpreted 82as a lower bound; if the kernel is unable to satisfy the request, the 83``PR_SET_TAGGED_ADDR_CTRL`` operation will fail. The actual number of tag bits 84is returned in ``PR_PMLEN`` by the ``PR_GET_TAGGED_ADDR_CTRL`` operation. 85 86Additionally, when pointer masking is enabled (``PR_PMLEN`` is greater than 0), 87a tagged address ABI is supported, with the same interface and behavior as 88documented for AArch64 (Documentation/arch/arm64/tagged-address-abi.rst). 89