xref: /linux/Documentation/arch/riscv/uabi.rst (revision 7f71507851fc7764b36a3221839607d3a45c2025)
1.. SPDX-License-Identifier: GPL-2.0
2
3RISC-V Linux User ABI
4=====================
5
6ISA string ordering in /proc/cpuinfo
7------------------------------------
8
9The canonical order of ISA extension names in the ISA string is defined in
10chapter 27 of the unprivileged specification.
11The specification uses vague wording, such as should, when it comes to ordering,
12so for our purposes the following rules apply:
13
14#. Single-letter extensions come first, in canonical order.
15   The canonical order is "IMAFDQLCBKJTPVH".
16
17#. All multi-letter extensions will be separated from other extensions by an
18   underscore.
19
20#. Additional standard extensions (starting with 'Z') will be sorted after
21   single-letter extensions and before any higher-privileged extensions.
22
23#. For additional standard extensions, the first letter following the 'Z'
24   conventionally indicates the most closely related alphabetical
25   extension category. If multiple 'Z' extensions are named, they will be
26   ordered first by category, in canonical order, as listed above, then
27   alphabetically within a category.
28
29#. Standard supervisor-level extensions (starting with 'S') will be listed
30   after standard unprivileged extensions.  If multiple supervisor-level
31   extensions are listed, they will be ordered alphabetically.
32
33#. Standard machine-level extensions (starting with 'Zxm') will be listed
34   after any lower-privileged, standard extensions. If multiple machine-level
35   extensions are listed, they will be ordered alphabetically.
36
37#. Non-standard extensions (starting with 'X') will be listed after all standard
38   extensions. If multiple non-standard extensions are listed, they will be
39   ordered alphabetically.
40
41An example string following the order is::
42
43   rv64imadc_zifoo_zigoo_zafoo_sbar_scar_zxmbaz_xqux_xrux
44
45"isa" and "hart isa" lines in /proc/cpuinfo
46-------------------------------------------
47
48The "isa" line in /proc/cpuinfo describes the lowest common denominator of
49RISC-V ISA extensions recognized by the kernel and implemented on all harts. The
50"hart isa" line, in contrast, describes the set of extensions recognized by the
51kernel on the particular hart being described, even if those extensions may not
52be present on all harts in the system.
53
54In both lines, the presence of an extension guarantees only that the hardware
55has the described capability. Additional kernel support or policy changes may be
56required before an extension's capability is fully usable by userspace programs.
57Similarly, for S-mode extensions, presence in one of these lines does not
58guarantee that the kernel is taking advantage of the extension, or that the
59feature will be visible in guest VMs managed by this kernel.
60
61Inversely, the absence of an extension in these lines does not necessarily mean
62the hardware does not support that feature. The running kernel may not recognize
63the extension, or may have deliberately removed it from the listing.
64
65Misaligned accesses
66-------------------
67
68Misaligned scalar accesses are supported in userspace, but they may perform
69poorly.  Misaligned vector accesses are only supported if the Zicclsm extension
70is supported.
71
72Pointer masking
73---------------
74
75Support for pointer masking in userspace (the Supm extension) is provided via
76the ``PR_SET_TAGGED_ADDR_CTRL`` and ``PR_GET_TAGGED_ADDR_CTRL`` ``prctl()``
77operations. Pointer masking is disabled by default. To enable it, userspace
78must call ``PR_SET_TAGGED_ADDR_CTRL`` with the ``PR_PMLEN`` field set to the
79number of mask/tag bits needed by the application. ``PR_PMLEN`` is interpreted
80as a lower bound; if the kernel is unable to satisfy the request, the
81``PR_SET_TAGGED_ADDR_CTRL`` operation will fail. The actual number of tag bits
82is returned in ``PR_PMLEN`` by the ``PR_GET_TAGGED_ADDR_CTRL`` operation.
83
84Additionally, when pointer masking is enabled (``PR_PMLEN`` is greater than 0),
85a tagged address ABI is supported, with the same interface and behavior as
86documented for AArch64 (Documentation/arch/arm64/tagged-address-abi.rst).
87