xref: /linux/Documentation/arch/powerpc/elf_hwcaps.rst (revision 5a4332062e9e71de8e78dc1b389d21e0dd44848b)
1.. _elf_hwcaps_powerpc:
2
3==================
4POWERPC ELF HWCAPs
5==================
6
7This document describes the usage and semantics of the powerpc ELF HWCAPs.
8
9
101. Introduction
11---------------
12
13Some hardware or software features are only available on some CPU
14implementations, and/or with certain kernel configurations, but have no other
15discovery mechanism available to userspace code. The kernel exposes the
16presence of these features to userspace through a set of flags called HWCAPs,
17exposed in the auxiliary vector.
18
19Userspace software can test for features by acquiring the AT_HWCAP or
20AT_HWCAP2 entry of the auxiliary vector, and testing whether the relevant
21flags are set, e.g.::
22
23	bool floating_point_is_present(void)
24	{
25		unsigned long HWCAPs = getauxval(AT_HWCAP);
26		if (HWCAPs & PPC_FEATURE_HAS_FPU)
27			return true;
28
29		return false;
30	}
31
32Where software relies on a feature described by a HWCAP, it should check the
33relevant HWCAP flag to verify that the feature is present before attempting to
34make use of the feature.
35
36HWCAP is the preferred method to test for the presence of a feature rather
37than probing through other means, which may not be reliable or may cause
38unpredictable behaviour.
39
40Software that targets a particular platform does not necessarily have to
41test for required or implied features. For example if the program requires
42FPU, VMX, VSX, it is not necessary to test those HWCAPs, and it may be
43impossible to do so if the compiler generates code requiring those features.
44
452. Facilities
46-------------
47
48The Power ISA uses the term "facility" to describe a class of instructions,
49registers, interrupts, etc. The presence or absence of a facility indicates
50whether this class is available to be used, but the specifics depend on the
51ISA version. For example, if the VSX facility is available, the VSX
52instructions that can be used differ between the v3.0B and v3.1B ISA
53versions.
54
553. Categories
56-------------
57
58The Power ISA before v3.0 uses the term "category" to describe certain
59classes of instructions and operating modes which may be optional or
60mutually exclusive, the exact meaning of the HWCAP flag may depend on
61context, e.g., the presence of the BOOKE feature implies that the server
62category is not implemented.
63
644. HWCAP allocation
65-------------------
66
67HWCAPs are allocated as described in Power Architecture 64-Bit ELF V2 ABI
68Specification (which will be reflected in the kernel's uapi headers).
69
705. The HWCAPs exposed in AT_HWCAP
71---------------------------------
72
73PPC_FEATURE_32
74    32-bit CPU
75
76PPC_FEATURE_64
77    64-bit CPU (userspace may be running in 32-bit mode).
78
79PPC_FEATURE_601_INSTR
80    The processor is PowerPC 601.
81    Unused in the kernel since f0ed73f3fa2c ("powerpc: Remove PowerPC 601")
82
83PPC_FEATURE_HAS_ALTIVEC
84    Vector (aka Altivec, VMX) facility is available.
85
86PPC_FEATURE_HAS_FPU
87    Floating point facility is available.
88
89PPC_FEATURE_HAS_MMU
90    Memory management unit is present and enabled.
91
92PPC_FEATURE_HAS_4xxMAC
93    The processor is 40x or 44x family.
94    Unused in the kernel since 732b32daef80 ("powerpc: Remove core support for 40x")
95
96PPC_FEATURE_UNIFIED_CACHE
97    The processor has a unified L1 cache for instructions and data, as
98    found in NXP e200.
99    Unused in the kernel since 39c8bf2b3cc1 ("powerpc: Retire e200 core (mpc555x processor)")
100
101PPC_FEATURE_HAS_SPE
102    Signal Processing Engine facility is available.
103
104PPC_FEATURE_HAS_EFP_SINGLE
105    Embedded Floating Point single precision operations are available.
106
107PPC_FEATURE_HAS_EFP_DOUBLE
108    Embedded Floating Point double precision operations are available.
109
110PPC_FEATURE_NO_TB
111    The timebase facility (mftb instruction) is not available.
112    This is a 601 specific HWCAP, so if it is known that the processor
113    running is not a 601, via other HWCAPs or other means, it is not
114    required to test this bit before using the timebase.
115    Unused in the kernel since f0ed73f3fa2c ("powerpc: Remove PowerPC 601")
116
117PPC_FEATURE_POWER4
118    The processor is POWER4 or PPC970/FX/MP.
119    POWER4 support dropped from the kernel since 471d7ff8b51b ("powerpc/64s: Remove POWER4 support")
120
121PPC_FEATURE_POWER5
122    The processor is POWER5.
123
124PPC_FEATURE_POWER5_PLUS
125    The processor is POWER5+.
126
127PPC_FEATURE_CELL
128    The processor is Cell.
129
130PPC_FEATURE_BOOKE
131    The processor implements the embedded category ("BookE") architecture.
132
133PPC_FEATURE_SMT
134    The processor implements SMT.
135
136PPC_FEATURE_ICACHE_SNOOP
137    The processor icache is coherent with the dcache, and instruction storage
138    can be made consistent with data storage for the purpose of executing
139    instructions with the sequence (as described in, e.g., POWER9 Processor
140    User's Manual, 4.6.2.2 Instruction Cache Block Invalidate (icbi))::
141
142        sync
143        icbi (to any address)
144        isync
145
146PPC_FEATURE_ARCH_2_05
147    The processor supports the v2.05 userlevel architecture. Processors
148    supporting later architectures DO NOT set this feature.
149
150PPC_FEATURE_PA6T
151    The processor is PA6T.
152
153PPC_FEATURE_HAS_DFP
154    DFP facility is available.
155
156PPC_FEATURE_POWER6_EXT
157    The processor is POWER6.
158
159PPC_FEATURE_ARCH_2_06
160    The processor supports the v2.06 userlevel architecture. Processors
161    supporting later architectures also set this feature.
162
163PPC_FEATURE_HAS_VSX
164    VSX facility is available.
165
166PPC_FEATURE_PSERIES_PERFMON_COMPAT
167    The processor supports architected PMU events in the range 0xE0-0xFF.
168
169PPC_FEATURE_TRUE_LE
170    The processor supports true little-endian mode.
171
172PPC_FEATURE_PPC_LE
173    The processor supports "PowerPC Little-Endian", that uses address
174    munging to make storage access appear to be little-endian, but the
175    data is stored in a different format that is unsuitable to be
176    accessed by other agents not running in this mode.
177
1786. The HWCAPs exposed in AT_HWCAP2
179----------------------------------
180
181PPC_FEATURE2_ARCH_2_07
182    The processor supports the v2.07 userlevel architecture. Processors
183    supporting later architectures also set this feature.
184
185PPC_FEATURE2_HTM
186    Transactional Memory feature is available.
187
188PPC_FEATURE2_DSCR
189    DSCR facility is available.
190
191PPC_FEATURE2_EBB
192    EBB facility is available.
193
194PPC_FEATURE2_ISEL
195    isel instruction is available. This is superseded by ARCH_2_07 and
196    later.
197
198PPC_FEATURE2_TAR
199    TAR facility is available.
200
201PPC_FEATURE2_VEC_CRYPTO
202    v2.07 crypto instructions are available.
203
204PPC_FEATURE2_HTM_NOSC
205    System calls fail if called in a transactional state, see
206    Documentation/arch/powerpc/syscall64-abi.rst
207
208PPC_FEATURE2_ARCH_3_00
209    The processor supports the v3.0B / v3.0C userlevel architecture. Processors
210    supporting later architectures also set this feature.
211
212PPC_FEATURE2_HAS_IEEE128
213    IEEE 128-bit binary floating point is supported with VSX
214    quad-precision instructions and data types.
215
216PPC_FEATURE2_DARN
217    darn instruction is available.
218
219PPC_FEATURE2_SCV
220    The scv 0 instruction may be used for system calls, see
221    Documentation/arch/powerpc/syscall64-abi.rst.
222
223PPC_FEATURE2_HTM_NO_SUSPEND
224    A limited Transactional Memory facility that does not support suspend is
225    available, see Documentation/arch/powerpc/transactional_memory.rst.
226
227PPC_FEATURE2_ARCH_3_1
228    The processor supports the v3.1 userlevel architecture. Processors
229    supporting later architectures also set this feature.
230
231PPC_FEATURE2_MMA
232    MMA facility is available.
233