xref: /linux/Documentation/arch/openrisc/openrisc_port.rst (revision 746680ec6696585e30db3e18c93a63df9cbec39c)
1==============
2OpenRISC Linux
3==============
4
5This is a port of Linux to the OpenRISC class of microprocessors; the initial
6target architecture, specifically, is the 32-bit OpenRISC 1000 family (or1k).
7
8For information about OpenRISC processors and ongoing development:
9
10	=======		==============================
11	website		https://openrisc.io
12	email		linux-openrisc@vger.kernel.org
13	=======		==============================
14
15---------------------------------------------------------------------
16
17Build instructions for OpenRISC toolchain and Linux
18===================================================
19
20In order to build and run Linux for OpenRISC, you'll need at least a basic
21toolchain and, perhaps, the architectural simulator.  Steps to get these bits
22in place are outlined here.
23
241) Toolchain
25
26Toolchain binaries can be obtained from openrisc.io or our github releases page.
27Instructions for building the different toolchains can be found on openrisc.io
28or Stafford's toolchain build and release scripts.
29
30	==========	==========================================================
31	binaries	https://github.com/stffrdhrn/or1k-toolchain-build/releases
32	toolchains	https://openrisc.io/software
33	building	https://github.com/stffrdhrn/or1k-toolchain-build
34	==========	==========================================================
35
362) Building
37
38Build the Linux kernel as usual::
39
40	make ARCH=openrisc CROSS_COMPILE="or1k-linux-" defconfig
41	make ARCH=openrisc CROSS_COMPILE="or1k-linux-"
42
43If you want to embed initramfs in the kernel, also pass ``CONFIG_INITRAMFS_SOURCE``. For example::
44
45	make ARCH=openrisc CROSS_COMPILE="or1k-linux-" CONFIG_INITRAMFS_SOURCE="path/to/rootfs path/to/devnodes"
46
47For more information on this, please check Documentation/filesystems/ramfs-rootfs-initramfs.rst.
48
493) Running on FPGA (optional)
50
51The OpenRISC community typically uses FuseSoC to manage building and programming
52an SoC into an FPGA.  The below is an example of programming a De0 Nano
53development board with the OpenRISC SoC.  During the build FPGA RTL is code
54downloaded from the FuseSoC IP cores repository and built using the FPGA vendor
55tools.  Binaries are loaded onto the board with openocd.
56
57::
58
59	git clone https://github.com/olofk/fusesoc
60	cd fusesoc
61	sudo pip install -e .
62
63	fusesoc init
64	fusesoc build de0_nano
65	fusesoc pgm de0_nano
66
67	openocd -f interface/altera-usb-blaster.cfg \
68		-f board/or1k_generic.cfg
69
70	telnet localhost 4444
71	> init
72	> halt; load_image vmlinux ; reset
73
744) Running on a Simulator (optional)
75
76QEMU is a processor emulator which we recommend for simulating the OpenRISC
77platform.  Please follow the OpenRISC instructions on the QEMU website to get
78Linux running on QEMU.  You can build QEMU yourself, but your Linux distribution
79likely provides binary packages to support OpenRISC.
80
81	=============	======================================================
82	qemu openrisc	https://wiki.qemu.org/Documentation/Platforms/OpenRISC
83	=============	======================================================
84
85---------------------------------------------------------------------
86
87Terminology
88===========
89
90In the code, the following particles are used on symbols to limit the scope
91to more or less specific processor implementations:
92
93========= =======================================
94openrisc: the OpenRISC class of processors
95or1k:     the OpenRISC 1000 family of processors
96or1200:   the OpenRISC 1200 processor
97========= =======================================
98
99---------------------------------------------------------------------
100
101History
102========
103
10418-11-2003	Matjaz Breskvar (phoenix@bsemi.com)
105	initial port of linux to OpenRISC/or32 architecture.
106        all the core stuff is implemented and seams usable.
107
10808-12-2003	Matjaz Breskvar (phoenix@bsemi.com)
109	complete change of TLB miss handling.
110	rewrite of exceptions handling.
111	fully functional sash-3.6 in default initrd.
112	a much improved version with changes all around.
113
11410-04-2004	Matjaz Breskvar (phoenix@bsemi.com)
115	a lot of bugfixes all over.
116	ethernet support, functional http and telnet servers.
117	running many standard linux apps.
118
11926-06-2004	Matjaz Breskvar (phoenix@bsemi.com)
120	port to 2.6.x
121
12230-11-2004	Matjaz Breskvar (phoenix@bsemi.com)
123	lots of bugfixes and enhancements.
124	added opencores framebuffer driver.
125
12609-10-2010    Jonas Bonn (jonas@southpole.se)
127	major rewrite to bring up to par with upstream Linux 2.6.36
128