1.. SPDX-License-Identifier: GPL-2.0 2 3======================================= 4IRQ chip model (hierarchy) of LoongArch 5======================================= 6 7Currently, LoongArch based processors (e.g. Loongson-3A5000) can only work together 8with LS7A chipsets. The irq chips in LoongArch computers include CPUINTC (CPU Core 9Interrupt Controller), LIOINTC (Legacy I/O Interrupt Controller), EIOINTC (Extended 10I/O Interrupt Controller), HTVECINTC (Hyper-Transport Vector Interrupt Controller), 11PCH-PIC (Main Interrupt Controller in LS7A chipset), PCH-LPC (LPC Interrupt Controller 12in LS7A chipset) and PCH-MSI (MSI Interrupt Controller). 13 14CPUINTC is a per-core controller (in CPU), LIOINTC/EIOINTC/HTVECINTC are per-package 15controllers (in CPU), while PCH-PIC/PCH-LPC/PCH-MSI are controllers out of CPU (i.e., 16in chipsets). These controllers (in other words, irqchips) are linked in a hierarchy, 17and there are two models of hierarchy (legacy model and extended model). 18 19Legacy IRQ model 20================ 21 22In this model, IPI (Inter-Processor Interrupt) and CPU Local Timer interrupt go 23to CPUINTC directly, CPU UARTS interrupts go to LIOINTC, while all other devices 24interrupts go to PCH-PIC/PCH-LPC/PCH-MSI and gathered by HTVECINTC, and then go 25to LIOINTC, and then CPUINTC:: 26 27 +-----+ +---------+ +-------+ 28 | IPI | --> | CPUINTC | <-- | Timer | 29 +-----+ +---------+ +-------+ 30 ^ 31 | 32 +---------+ +-------+ 33 | LIOINTC | <-- | UARTs | 34 +---------+ +-------+ 35 ^ 36 | 37 +-----------+ 38 | HTVECINTC | 39 +-----------+ 40 ^ ^ 41 | | 42 +---------+ +---------+ 43 | PCH-PIC | | PCH-MSI | 44 +---------+ +---------+ 45 ^ ^ ^ 46 | | | 47 +---------+ +---------+ +---------+ 48 | PCH-LPC | | Devices | | Devices | 49 +---------+ +---------+ +---------+ 50 ^ 51 | 52 +---------+ 53 | Devices | 54 +---------+ 55 56Extended IRQ model 57================== 58 59In this model, IPI (Inter-Processor Interrupt) and CPU Local Timer interrupt go 60to CPUINTC directly, CPU UARTS interrupts go to LIOINTC, while all other devices 61interrupts go to PCH-PIC/PCH-LPC/PCH-MSI and gathered by EIOINTC, and then go to 62to CPUINTC directly:: 63 64 +-----+ +---------+ +-------+ 65 | IPI | --> | CPUINTC | <-- | Timer | 66 +-----+ +---------+ +-------+ 67 ^ ^ 68 | | 69 +---------+ +---------+ +-------+ 70 | EIOINTC | | LIOINTC | <-- | UARTs | 71 +---------+ +---------+ +-------+ 72 ^ ^ 73 | | 74 +---------+ +---------+ 75 | PCH-PIC | | PCH-MSI | 76 +---------+ +---------+ 77 ^ ^ ^ 78 | | | 79 +---------+ +---------+ +---------+ 80 | PCH-LPC | | Devices | | Devices | 81 +---------+ +---------+ +---------+ 82 ^ 83 | 84 +---------+ 85 | Devices | 86 +---------+ 87 88Virtual Extended IRQ model 89========================== 90 91In this model, IPI (Inter-Processor Interrupt) and CPU Local Timer interrupt 92go to CPUINTC directly, CPU UARTS interrupts go to PCH-PIC, while all other 93devices interrupts go to PCH-PIC/PCH-MSI and gathered by V-EIOINTC (Virtual 94Extended I/O Interrupt Controller), and then go to CPUINTC directly:: 95 96 +-----+ +-------------------+ +-------+ 97 | IPI |--> | CPUINTC(0-255vcpu)| <-- | Timer | 98 +-----+ +-------------------+ +-------+ 99 ^ 100 | 101 +-----------+ 102 | V-EIOINTC | 103 +-----------+ 104 ^ ^ 105 | | 106 +---------+ +---------+ 107 | PCH-PIC | | PCH-MSI | 108 +---------+ +---------+ 109 ^ ^ ^ 110 | | | 111 +--------+ +---------+ +---------+ 112 | UARTs | | Devices | | Devices | 113 +--------+ +---------+ +---------+ 114 115 116Description 117----------- 118V-EIOINTC (Virtual Extended I/O Interrupt Controller) is an extension of 119EIOINTC, it only works in VM mode which runs in KVM hypervisor. Interrupts can 120be routed to up to four vCPUs via standard EIOINTC, however with V-EIOINTC 121interrupts can be routed to up to 256 virtual cpus. 122 123With standard EIOINTC, interrupt routing setting includes two parts: eight 124bits for CPU selection and four bits for CPU IP (Interrupt Pin) selection. 125For CPU selection there is four bits for EIOINTC node selection, four bits 126for EIOINTC CPU selection. Bitmap method is used for CPU selection and 127CPU IP selection, so interrupt can only route to CPU0 - CPU3 and IP0-IP3 in 128one EIOINTC node. 129 130With V-EIOINTC it supports to route more CPUs and CPU IP (Interrupt Pin), 131there are two newly added registers with V-EIOINTC. 132 133EXTIOI_VIRT_FEATURES 134-------------------- 135This register is read-only register, which indicates supported features with 136V-EIOINTC. Feature EXTIOI_HAS_INT_ENCODE and EXTIOI_HAS_CPU_ENCODE is added. 137 138Feature EXTIOI_HAS_INT_ENCODE is part of standard EIOINTC. If it is 1, it 139indicates that CPU Interrupt Pin selection can be normal method rather than 140bitmap method, so interrupt can be routed to IP0 - IP15. 141 142Feature EXTIOI_HAS_CPU_ENCODE is entension of V-EIOINTC. If it is 1, it 143indicates that CPU selection can be normal method rather than bitmap method, 144so interrupt can be routed to CPU0 - CPU255. 145 146EXTIOI_VIRT_CONFIG 147------------------ 148This register is read-write register, for compatibility intterupt routed uses 149the default method which is the same with standard EIOINTC. If the bit is set 150with 1, it indicated HW to use normal method rather than bitmap method. 151 152Advanced Extended IRQ model 153=========================== 154 155In this model, IPI (Inter-Processor Interrupt) and CPU Local Timer interrupt go 156to CPUINTC directly, CPU UARTS interrupts go to LIOINTC, PCH-MSI interrupts go 157to AVECINTC, and then go to CPUINTC directly, while all other devices interrupts 158go to PCH-PIC/PCH-LPC and gathered by EIOINTC, and then go to CPUINTC directly:: 159 160 +-----+ +-----------------------+ +-------+ 161 | IPI | --> | CPUINTC | <-- | Timer | 162 +-----+ +-----------------------+ +-------+ 163 ^ ^ ^ 164 | | | 165 +---------+ +----------+ +---------+ +-------+ 166 | EIOINTC | | AVECINTC | | LIOINTC | <-- | UARTs | 167 +---------+ +----------+ +---------+ +-------+ 168 ^ ^ 169 | | 170 +---------+ +---------+ 171 | PCH-PIC | | PCH-MSI | 172 +---------+ +---------+ 173 ^ ^ ^ 174 | | | 175 +---------+ +---------+ +---------+ 176 | Devices | | PCH-LPC | | Devices | 177 +---------+ +---------+ +---------+ 178 ^ 179 | 180 +---------+ 181 | Devices | 182 +---------+ 183 184ACPI-related definitions 185======================== 186 187CPUINTC:: 188 189 ACPI_MADT_TYPE_CORE_PIC; 190 struct acpi_madt_core_pic; 191 enum acpi_madt_core_pic_version; 192 193LIOINTC:: 194 195 ACPI_MADT_TYPE_LIO_PIC; 196 struct acpi_madt_lio_pic; 197 enum acpi_madt_lio_pic_version; 198 199EIOINTC:: 200 201 ACPI_MADT_TYPE_EIO_PIC; 202 struct acpi_madt_eio_pic; 203 enum acpi_madt_eio_pic_version; 204 205HTVECINTC:: 206 207 ACPI_MADT_TYPE_HT_PIC; 208 struct acpi_madt_ht_pic; 209 enum acpi_madt_ht_pic_version; 210 211PCH-PIC:: 212 213 ACPI_MADT_TYPE_BIO_PIC; 214 struct acpi_madt_bio_pic; 215 enum acpi_madt_bio_pic_version; 216 217PCH-MSI:: 218 219 ACPI_MADT_TYPE_MSI_PIC; 220 struct acpi_madt_msi_pic; 221 enum acpi_madt_msi_pic_version; 222 223PCH-LPC:: 224 225 ACPI_MADT_TYPE_LPC_PIC; 226 struct acpi_madt_lpc_pic; 227 enum acpi_madt_lpc_pic_version; 228 229References 230========== 231 232Documentation of Loongson-3A5000: 233 234 https://github.com/loongson/LoongArch-Documentation/releases/latest/download/Loongson-3A5000-usermanual-1.02-CN.pdf (in Chinese) 235 236 https://github.com/loongson/LoongArch-Documentation/releases/latest/download/Loongson-3A5000-usermanual-1.02-EN.pdf (in English) 237 238Documentation of Loongson's LS7A chipset: 239 240 https://github.com/loongson/LoongArch-Documentation/releases/latest/download/Loongson-7A1000-usermanual-2.00-CN.pdf (in Chinese) 241 242 https://github.com/loongson/LoongArch-Documentation/releases/latest/download/Loongson-7A1000-usermanual-2.00-EN.pdf (in English) 243 244.. Note:: 245 - CPUINTC is CSR.ECFG/CSR.ESTAT and its interrupt controller described 246 in Section 7.4 of "LoongArch Reference Manual, Vol 1"; 247 - LIOINTC is "Legacy I/OInterrupts" described in Section 11.1 of 248 "Loongson 3A5000 Processor Reference Manual"; 249 - EIOINTC is "Extended I/O Interrupts" described in Section 11.2 of 250 "Loongson 3A5000 Processor Reference Manual"; 251 - HTVECINTC is "HyperTransport Interrupts" described in Section 14.3 of 252 "Loongson 3A5000 Processor Reference Manual"; 253 - PCH-PIC/PCH-MSI is "Interrupt Controller" described in Section 5 of 254 "Loongson 7A1000 Bridge User Manual"; 255 - PCH-LPC is "LPC Interrupts" described in Section 24.3 of 256 "Loongson 7A1000 Bridge User Manual". 257