1*4ce0a2ccSBen Horgan.. SPDX-License-Identifier: GPL-2.0 2*4ce0a2ccSBen Horgan 3*4ce0a2ccSBen Horgan==== 4*4ce0a2ccSBen HorganMPAM 5*4ce0a2ccSBen Horgan==== 6*4ce0a2ccSBen Horgan 7*4ce0a2ccSBen HorganWhat is MPAM 8*4ce0a2ccSBen Horgan============ 9*4ce0a2ccSBen HorganMPAM (Memory Partitioning and Monitoring) is a feature in the CPUs and memory 10*4ce0a2ccSBen Horgansystem components such as the caches or memory controllers that allow memory 11*4ce0a2ccSBen Horgantraffic to be labelled, partitioned and monitored. 12*4ce0a2ccSBen Horgan 13*4ce0a2ccSBen HorganTraffic is labelled by the CPU, based on the control or monitor group the 14*4ce0a2ccSBen Horgancurrent task is assigned to using resctrl. Partitioning policy can be set 15*4ce0a2ccSBen Horganusing the schemata file in resctrl, and monitor values read via resctrl. 16*4ce0a2ccSBen HorganSee Documentation/filesystems/resctrl.rst for more details. 17*4ce0a2ccSBen Horgan 18*4ce0a2ccSBen HorganThis allows tasks that share memory system resources, such as caches, to be 19*4ce0a2ccSBen Horganisolated from each other according to the partitioning policy (so called noisy 20*4ce0a2ccSBen Horganneighbours). 21*4ce0a2ccSBen Horgan 22*4ce0a2ccSBen HorganSupported Platforms 23*4ce0a2ccSBen Horgan=================== 24*4ce0a2ccSBen HorganUse of this feature requires CPU support, support in the memory system 25*4ce0a2ccSBen Horgancomponents, and a description from firmware of where the MPAM device controls 26*4ce0a2ccSBen Horganare in the MMIO address space. (e.g. the 'MPAM' ACPI table). 27*4ce0a2ccSBen Horgan 28*4ce0a2ccSBen HorganThe MMIO device that provides MPAM controls/monitors for a memory system 29*4ce0a2ccSBen Horgancomponent is called a memory system component. (MSC). 30*4ce0a2ccSBen Horgan 31*4ce0a2ccSBen HorganBecause the user interface to MPAM is via resctrl, only MPAM features that are 32*4ce0a2ccSBen Horgancompatible with resctrl can be exposed to user-space. 33*4ce0a2ccSBen Horgan 34*4ce0a2ccSBen HorganMSC are considered as a group based on the topology. MSC that correspond with 35*4ce0a2ccSBen Horganthe L3 cache are considered together, it is not possible to mix MSC between L2 36*4ce0a2ccSBen Horganand L3 to 'cover' a resctrl schema. 37*4ce0a2ccSBen Horgan 38*4ce0a2ccSBen HorganThe supported features are: 39*4ce0a2ccSBen Horgan 40*4ce0a2ccSBen Horgan* Cache portion bitmap controls (CPOR) on the L2 or L3 caches. To expose 41*4ce0a2ccSBen Horgan CPOR at L2 or L3, every CPU must have a corresponding CPU cache at this 42*4ce0a2ccSBen Horgan level that also supports the feature. Mismatched big/little platforms are 43*4ce0a2ccSBen Horgan not supported as resctrl's controls would then also depend on task 44*4ce0a2ccSBen Horgan placement. 45*4ce0a2ccSBen Horgan 46*4ce0a2ccSBen Horgan* Memory bandwidth maximum controls (MBW_MAX) on or after the L3 cache. 47*4ce0a2ccSBen Horgan resctrl uses the L3 cache-id to identify where the memory bandwidth 48*4ce0a2ccSBen Horgan control is applied. For this reason the platform must have an L3 cache 49*4ce0a2ccSBen Horgan with cache-id's supplied by firmware. (It doesn't need to support MPAM.) 50*4ce0a2ccSBen Horgan 51*4ce0a2ccSBen Horgan To be exported as the 'MB' schema, the topology of the group of MSC chosen 52*4ce0a2ccSBen Horgan must match the topology of the L3 cache so that the cache-id's can be 53*4ce0a2ccSBen Horgan repainted. For example: Platforms with Memory bandwidth maximum controls 54*4ce0a2ccSBen Horgan on CPU-less NUMA nodes cannot expose the 'MB' schema to resctrl as these 55*4ce0a2ccSBen Horgan nodes do not have a corresponding L3 cache. If the memory bandwidth 56*4ce0a2ccSBen Horgan control is on the memory rather than the L3 then there must be a single 57*4ce0a2ccSBen Horgan global L3 as otherwise it is unknown which L3 the traffic came from. There 58*4ce0a2ccSBen Horgan must be no caches between the L3 and the memory so that the two ends of 59*4ce0a2ccSBen Horgan the path have equivalent traffic. 60*4ce0a2ccSBen Horgan 61*4ce0a2ccSBen Horgan When the MPAM driver finds multiple groups of MSC it can use for the 'MB' 62*4ce0a2ccSBen Horgan schema, it prefers the group closest to the L3 cache. 63*4ce0a2ccSBen Horgan 64*4ce0a2ccSBen Horgan* Cache Storage Usage (CSU) counters can expose the 'llc_occupancy' provided 65*4ce0a2ccSBen Horgan there is at least one CSU monitor on each MSC that makes up the L3 group. 66*4ce0a2ccSBen Horgan Exposing CSU counters from other caches or devices is not supported. 67*4ce0a2ccSBen Horgan 68*4ce0a2ccSBen HorganReporting Bugs 69*4ce0a2ccSBen Horgan============== 70*4ce0a2ccSBen HorganIf you are not seeing the counters or controls you expect please share the 71*4ce0a2ccSBen Horgandebug messages produced when enabling dynamic debug and booting with: 72*4ce0a2ccSBen Horgandyndbg="file mpam_resctrl.c +pl" 73