1.. SPDX-License-Identifier: GPL-2.0 2 3=================================== 4Memory copy/set instructions (MOPS) 5=================================== 6 7A MOPS memory copy/set operation consists of three consecutive CPY* or SET* 8instructions: a prologue, main and epilogue (for example: CPYP, CPYM, CPYE). 9 10A main or epilogue instruction can take a MOPS exception for various reasons, 11for example when a task is migrated to a CPU with a different MOPS 12implementation, or when the instruction's alignment and size requirements are 13not met. The software exception handler is then expected to reset the registers 14and restart execution from the prologue instruction. Normally this is handled 15by the kernel. 16 17For more details refer to "D1.3.5.7 Memory Copy and Memory Set exceptions" in 18the Arm Architecture Reference Manual DDI 0487K.a (Arm ARM). 19 20.. _arm64_mops_hyp: 21 22Hypervisor requirements 23----------------------- 24 25A hypervisor running a Linux guest must handle all MOPS exceptions from the 26guest kernel, as Linux may not be able to handle the exception at all times. 27For example, a MOPS exception can be taken when the hypervisor migrates a vCPU 28to another physical CPU with a different MOPS implementation. 29 30To do this, the hypervisor must: 31 32 - Set HCRX_EL2.MCE2 to 1 so that the exception is taken to the hypervisor. 33 34 - Have an exception handler that implements the algorithm from the Arm ARM 35 rules CNTMJ and MWFQH. 36 37 - Set the guest's PSTATE.SS to 0 in the exception handler, to handle a 38 potential step of the current instruction. 39 40 Note: Clearing PSTATE.SS is needed so that a single step exception is taken 41 on the next instruction (the prologue instruction). Otherwise prologue 42 would get silently stepped over and the single step exception taken on the 43 main instruction. Note that if the guest instruction is not being stepped 44 then clearing PSTATE.SS has no effect. 45