xref: /linux/Documentation/arch/arm64/elf_hwcaps.rst (revision 8838a1a2d219a86ab05e679c73f68dd75a25aca5) 
1.. _elf_hwcaps_index:
2
3================
4ARM64 ELF hwcaps
5================
6
7This document describes the usage and semantics of the arm64 ELF hwcaps.
8
9
101. Introduction
11---------------
12
13Some hardware or software features are only available on some CPU
14implementations, and/or with certain kernel configurations, but have no
15architected discovery mechanism available to userspace code at EL0. The
16kernel exposes the presence of these features to userspace through a set
17of flags called hwcaps, exposed in the auxiliary vector.
18
19Userspace software can test for features by acquiring the AT_HWCAP,
20AT_HWCAP2 or AT_HWCAP3 entry of the auxiliary vector, and testing
21whether the relevant flags are set, e.g.::
22
23	bool floating_point_is_present(void)
24	{
25		unsigned long hwcaps = getauxval(AT_HWCAP);
26		if (hwcaps & HWCAP_FP)
27			return true;
28
29		return false;
30	}
31
32Where software relies on a feature described by a hwcap, it should check
33the relevant hwcap flag to verify that the feature is present before
34attempting to make use of the feature.
35
36Features cannot be probed reliably through other means. When a feature
37is not available, attempting to use it may result in unpredictable
38behaviour, and is not guaranteed to result in any reliable indication
39that the feature is unavailable, such as a SIGILL.
40
41
422. Interpretation of hwcaps
43---------------------------
44
45The majority of hwcaps are intended to indicate the presence of features
46which are described by architected ID registers inaccessible to
47userspace code at EL0. These hwcaps are defined in terms of ID register
48fields, and should be interpreted with reference to the definition of
49these fields in the ARM Architecture Reference Manual (ARM ARM).
50
51Such hwcaps are described below in the form::
52
53    Functionality implied by idreg.field == val.
54
55Such hwcaps indicate the availability of functionality that the ARM ARM
56defines as being present when idreg.field has value val, but do not
57indicate that idreg.field is precisely equal to val, nor do they
58indicate the absence of functionality implied by other values of
59idreg.field.
60
61Other hwcaps may indicate the presence of features which cannot be
62described by ID registers alone. These may be described without
63reference to ID registers, and may refer to other documentation.
64
65
663. The hwcaps exposed in AT_HWCAP
67---------------------------------
68
69HWCAP_FP
70    Functionality implied by ID_AA64PFR0_EL1.FP == 0b0000.
71
72HWCAP_ASIMD
73    Functionality implied by ID_AA64PFR0_EL1.AdvSIMD == 0b0000.
74
75HWCAP_EVTSTRM
76    The generic timer is configured to generate events at a frequency of
77    approximately 10KHz.
78
79HWCAP_AES
80    Functionality implied by ID_AA64ISAR0_EL1.AES == 0b0001.
81
82HWCAP_PMULL
83    Functionality implied by ID_AA64ISAR0_EL1.AES == 0b0010.
84
85HWCAP_SHA1
86    Functionality implied by ID_AA64ISAR0_EL1.SHA1 == 0b0001.
87
88HWCAP_SHA2
89    Functionality implied by ID_AA64ISAR0_EL1.SHA2 == 0b0001.
90
91HWCAP_CRC32
92    Functionality implied by ID_AA64ISAR0_EL1.CRC32 == 0b0001.
93
94HWCAP_ATOMICS
95    Functionality implied by ID_AA64ISAR0_EL1.Atomic == 0b0010.
96
97HWCAP_FPHP
98    Functionality implied by ID_AA64PFR0_EL1.FP == 0b0001.
99
100HWCAP_ASIMDHP
101    Functionality implied by ID_AA64PFR0_EL1.AdvSIMD == 0b0001.
102
103HWCAP_CPUID
104    EL0 access to certain ID registers is available, to the extent
105    described by Documentation/arch/arm64/cpu-feature-registers.rst.
106
107    These ID registers may imply the availability of features.
108
109HWCAP_ASIMDRDM
110    Functionality implied by ID_AA64ISAR0_EL1.RDM == 0b0001.
111
112HWCAP_JSCVT
113    Functionality implied by ID_AA64ISAR1_EL1.JSCVT == 0b0001.
114
115HWCAP_FCMA
116    Functionality implied by ID_AA64ISAR1_EL1.FCMA == 0b0001.
117
118HWCAP_LRCPC
119    Functionality implied by ID_AA64ISAR1_EL1.LRCPC == 0b0001.
120
121HWCAP_DCPOP
122    Functionality implied by ID_AA64ISAR1_EL1.DPB == 0b0001.
123
124HWCAP_SHA3
125    Functionality implied by ID_AA64ISAR0_EL1.SHA3 == 0b0001.
126
127HWCAP_SM3
128    Functionality implied by ID_AA64ISAR0_EL1.SM3 == 0b0001.
129
130HWCAP_SM4
131    Functionality implied by ID_AA64ISAR0_EL1.SM4 == 0b0001.
132
133HWCAP_ASIMDDP
134    Functionality implied by ID_AA64ISAR0_EL1.DP == 0b0001.
135
136HWCAP_SHA512
137    Functionality implied by ID_AA64ISAR0_EL1.SHA2 == 0b0010.
138
139HWCAP_SVE
140    Functionality implied by ID_AA64PFR0_EL1.SVE == 0b0001.
141
142HWCAP_ASIMDFHM
143   Functionality implied by ID_AA64ISAR0_EL1.FHM == 0b0001.
144
145HWCAP_DIT
146    Functionality implied by ID_AA64PFR0_EL1.DIT == 0b0001.
147
148HWCAP_USCAT
149    Functionality implied by ID_AA64MMFR2_EL1.AT == 0b0001.
150
151HWCAP_ILRCPC
152    Functionality implied by ID_AA64ISAR1_EL1.LRCPC == 0b0010.
153
154HWCAP_FLAGM
155    Functionality implied by ID_AA64ISAR0_EL1.TS == 0b0001.
156
157HWCAP_SSBS
158    Functionality implied by ID_AA64PFR1_EL1.SSBS == 0b0010.
159
160HWCAP_SB
161    Functionality implied by ID_AA64ISAR1_EL1.SB == 0b0001.
162
163HWCAP_PACA
164    Functionality implied by ID_AA64ISAR1_EL1.APA == 0b0001 or
165    ID_AA64ISAR1_EL1.API == 0b0001, as described by
166    Documentation/arch/arm64/pointer-authentication.rst.
167
168HWCAP_PACG
169    Functionality implied by ID_AA64ISAR1_EL1.GPA == 0b0001 or
170    ID_AA64ISAR1_EL1.GPI == 0b0001, as described by
171    Documentation/arch/arm64/pointer-authentication.rst.
172
173HWCAP_GCS
174    Functionality implied by ID_AA64PFR1_EL1.GCS == 0b1, as
175    described by Documentation/arch/arm64/gcs.rst.
176
177HWCAP_CMPBR
178    Functionality implied by ID_AA64ISAR2_EL1.CSSC == 0b0010.
179
180HWCAP_FPRCVT
181    Functionality implied by ID_AA64ISAR3_EL1.FPRCVT == 0b0001.
182
183HWCAP_F8MM8
184    Functionality implied by ID_AA64FPFR0_EL1.F8MM8 == 0b0001.
185
186HWCAP_F8MM4
187    Functionality implied by ID_AA64FPFR0_EL1.F8MM4 == 0b0001.
188
189HWCAP_SVE_F16MM
190    Functionality implied by ID_AA64PFR0_EL1.SVE == 0b0001 and
191    ID_AA64ZFR0_EL1.F16MM == 0b0001.
192
193HWCAP_SVE_ELTPERM
194    Functionality implied by ID_AA64PFR0_EL1.SVE == 0b0001 and
195    ID_AA64ZFR0_EL1.ELTPERM == 0b0001.
196
197HWCAP_SVE_AES2
198    Functionality implied by ID_AA64PFR0_EL1.SVE == 0b0001 and
199    ID_AA64ZFR0_EL1.AES == 0b0011.
200
201HWCAP_SVE_BFSCALE
202    Functionality implied by ID_AA64PFR0_EL1.SVE == 0b0001 and
203    ID_AA64ZFR0_EL1.B16B16 == 0b0010.
204
205HWCAP_SVE2P2
206    Functionality implied by ID_AA64PFR0_EL1.SVE == 0b0001 and
207    ID_AA64ZFR0_EL1.SVEver == 0b0011.
208
209HWCAP_SME2P2
210    Functionality implied by ID_AA64SMFR0_EL1.SMEver == 0b0011.
211
212HWCAP_SME_SBITPERM
213    Functionality implied by ID_AA64SMFR0_EL1.SBitPerm == 0b1.
214
215HWCAP_SME_AES
216    Functionality implied by ID_AA64SMFR0_EL1.AES == 0b1.
217
218HWCAP_SME_SFEXPA
219    Functionality implied by ID_AA64SMFR0_EL1.SFEXPA == 0b1.
220
221HWCAP_SME_STMOP
222    Functionality implied by ID_AA64SMFR0_EL1.STMOP == 0b1.
223
224HWCAP_SME_SMOP4
225    Functionality implied by ID_AA64SMFR0_EL1.SMOP4 == 0b1.
226
227HWCAP2_DCPODP
228    Functionality implied by ID_AA64ISAR1_EL1.DPB == 0b0010.
229
230HWCAP2_SVE2
231    Functionality implied by ID_AA64PFR0_EL1.SVE == 0b0001 and
232    ID_AA64ZFR0_EL1.SVEver == 0b0001.
233
234HWCAP2_SVEAES
235    Functionality implied by ID_AA64PFR0_EL1.SVE == 0b0001 and
236    ID_AA64ZFR0_EL1.AES == 0b0001.
237
238HWCAP2_SVEPMULL
239    Functionality implied by ID_AA64PFR0_EL1.SVE == 0b0001 and
240    ID_AA64ZFR0_EL1.AES == 0b0010.
241
242HWCAP2_SVEBITPERM
243    Functionality implied by ID_AA64PFR0_EL1.SVE == 0b0001 and
244    ID_AA64ZFR0_EL1.BitPerm == 0b0001.
245
246HWCAP2_SVESHA3
247    Functionality implied by ID_AA64PFR0_EL1.SVE == 0b0001 and
248    ID_AA64ZFR0_EL1.SHA3 == 0b0001.
249
250HWCAP2_SVESM4
251    Functionality implied by ID_AA64PFR0_EL1.SVE == 0b0001 and
252    ID_AA64ZFR0_EL1.SM4 == 0b0001.
253
254HWCAP2_FLAGM2
255    Functionality implied by ID_AA64ISAR0_EL1.TS == 0b0010.
256
257HWCAP2_FRINT
258    Functionality implied by ID_AA64ISAR1_EL1.FRINTTS == 0b0001.
259
260HWCAP2_SVEI8MM
261    Functionality implied by ID_AA64PFR0_EL1.SVE == 0b0001 and
262    ID_AA64ZFR0_EL1.I8MM == 0b0001.
263
264HWCAP2_SVEF32MM
265    Functionality implied by ID_AA64PFR0_EL1.SVE == 0b0001 and
266    ID_AA64ZFR0_EL1.F32MM == 0b0001.
267
268HWCAP2_SVEF64MM
269    Functionality implied by ID_AA64PFR0_EL1.SVE == 0b0001 and
270    ID_AA64ZFR0_EL1.F64MM == 0b0001.
271
272HWCAP2_SVEBF16
273    Functionality implied by ID_AA64PFR0_EL1.SVE == 0b0001 and
274    ID_AA64ZFR0_EL1.BF16 == 0b0001.
275
276HWCAP2_I8MM
277    Functionality implied by ID_AA64ISAR1_EL1.I8MM == 0b0001.
278
279HWCAP2_BF16
280    Functionality implied by ID_AA64ISAR1_EL1.BF16 == 0b0001.
281
282HWCAP2_DGH
283    Functionality implied by ID_AA64ISAR1_EL1.DGH == 0b0001.
284
285HWCAP2_RNG
286    Functionality implied by ID_AA64ISAR0_EL1.RNDR == 0b0001.
287
288HWCAP2_BTI
289    Functionality implied by ID_AA64PFR1_EL1.BT == 0b0001.
290
291HWCAP2_MTE
292    Functionality implied by ID_AA64PFR1_EL1.MTE == 0b0010, as described
293    by Documentation/arch/arm64/memory-tagging-extension.rst.
294
295HWCAP2_ECV
296    Functionality implied by ID_AA64MMFR0_EL1.ECV == 0b0001.
297
298HWCAP2_AFP
299    Functionality implied by ID_AA64MMFR1_EL1.AFP == 0b0001.
300
301HWCAP2_RPRES
302    Functionality implied by ID_AA64ISAR2_EL1.RPRES == 0b0001.
303
304HWCAP2_MTE3
305    Functionality implied by ID_AA64PFR1_EL1.MTE == 0b0011, as described
306    by Documentation/arch/arm64/memory-tagging-extension.rst.
307
308HWCAP2_SME
309    Functionality implied by ID_AA64PFR1_EL1.SME == 0b0001, as described
310    by Documentation/arch/arm64/sme.rst.
311
312HWCAP2_SME_I16I64
313    Functionality implied by ID_AA64SMFR0_EL1.I16I64 == 0b1111.
314
315HWCAP2_SME_F64F64
316    Functionality implied by ID_AA64SMFR0_EL1.F64F64 == 0b1.
317
318HWCAP2_SME_I8I32
319    Functionality implied by ID_AA64SMFR0_EL1.I8I32 == 0b1111.
320
321HWCAP2_SME_F16F32
322    Functionality implied by ID_AA64SMFR0_EL1.F16F32 == 0b1.
323
324HWCAP2_SME_B16F32
325    Functionality implied by ID_AA64SMFR0_EL1.B16F32 == 0b1.
326
327HWCAP2_SME_F32F32
328    Functionality implied by ID_AA64SMFR0_EL1.F32F32 == 0b1.
329
330HWCAP2_SME_FA64
331    Functionality implied by ID_AA64SMFR0_EL1.FA64 == 0b1.
332
333HWCAP2_WFXT
334    Functionality implied by ID_AA64ISAR2_EL1.WFXT == 0b0010.
335
336HWCAP2_EBF16
337    Functionality implied by ID_AA64ISAR1_EL1.BF16 == 0b0010.
338
339HWCAP2_SVE_EBF16
340    Functionality implied by ID_AA64PFR0_EL1.SVE == 0b0001 and
341    ID_AA64ZFR0_EL1.BF16 == 0b0010.
342
343HWCAP2_CSSC
344    Functionality implied by ID_AA64ISAR2_EL1.CSSC == 0b0001.
345
346HWCAP2_RPRFM
347    Functionality implied by ID_AA64ISAR2_EL1.RPRFM == 0b0001.
348
349HWCAP2_SVE2P1
350    Functionality implied by ID_AA64PFR0_EL1.SVE == 0b0001 and
351    ID_AA64ZFR0_EL1.SVEver == 0b0010.
352
353HWCAP2_SME2
354    Functionality implied by ID_AA64SMFR0_EL1.SMEver == 0b0001.
355
356HWCAP2_SME2P1
357    Functionality implied by ID_AA64SMFR0_EL1.SMEver == 0b0010.
358
359HWCAP2_SMEI16I32
360    Functionality implied by ID_AA64SMFR0_EL1.I16I32 == 0b0101
361
362HWCAP2_SMEBI32I32
363    Functionality implied by ID_AA64SMFR0_EL1.BI32I32 == 0b1
364
365HWCAP2_SMEB16B16
366    Functionality implied by ID_AA64SMFR0_EL1.B16B16 == 0b1
367
368HWCAP2_SMEF16F16
369    Functionality implied by ID_AA64SMFR0_EL1.F16F16 == 0b1
370
371HWCAP2_MOPS
372    Functionality implied by ID_AA64ISAR2_EL1.MOPS == 0b0001.
373
374HWCAP2_HBC
375    Functionality implied by ID_AA64ISAR2_EL1.BC == 0b0001.
376
377HWCAP2_SVE_B16B16
378    Functionality implied by ID_AA64PFR0_EL1.SVE == 0b0001 and
379    ID_AA64ZFR0_EL1.B16B16 == 0b0001.
380
381HWCAP2_LRCPC3
382    Functionality implied by ID_AA64ISAR1_EL1.LRCPC == 0b0011.
383
384HWCAP2_LSE128
385    Functionality implied by ID_AA64ISAR0_EL1.Atomic == 0b0011.
386
387HWCAP2_FPMR
388    Functionality implied by ID_AA64PFR2_EL1.FMR == 0b0001.
389
390HWCAP2_LUT
391    Functionality implied by ID_AA64ISAR2_EL1.LUT == 0b0001.
392
393HWCAP2_FAMINMAX
394    Functionality implied by ID_AA64ISAR3_EL1.FAMINMAX == 0b0001.
395
396HWCAP2_F8CVT
397    Functionality implied by ID_AA64FPFR0_EL1.F8CVT == 0b1.
398
399HWCAP2_F8FMA
400    Functionality implied by ID_AA64FPFR0_EL1.F8FMA == 0b1.
401
402HWCAP2_F8DP4
403    Functionality implied by ID_AA64FPFR0_EL1.F8DP4 == 0b1.
404
405HWCAP2_F8DP2
406    Functionality implied by ID_AA64FPFR0_EL1.F8DP2 == 0b1.
407
408HWCAP2_F8E4M3
409    Functionality implied by ID_AA64FPFR0_EL1.F8E4M3 == 0b1.
410
411HWCAP2_F8E5M2
412    Functionality implied by ID_AA64FPFR0_EL1.F8E5M2 == 0b1.
413
414HWCAP2_SME_LUTV2
415    Functionality implied by ID_AA64SMFR0_EL1.LUTv2 == 0b1.
416
417HWCAP2_SME_F8F16
418    Functionality implied by ID_AA64SMFR0_EL1.F8F16 == 0b1.
419
420HWCAP2_SME_F8F32
421    Functionality implied by ID_AA64SMFR0_EL1.F8F32 == 0b1.
422
423HWCAP2_SME_SF8FMA
424    Functionality implied by ID_AA64SMFR0_EL1.SF8FMA == 0b1.
425
426HWCAP2_SME_SF8DP4
427    Functionality implied by ID_AA64SMFR0_EL1.SF8DP4 == 0b1.
428
429HWCAP2_SME_SF8DP2
430    Functionality implied by ID_AA64SMFR0_EL1.SF8DP2 == 0b1.
431
432HWCAP2_SME_SF8DP4
433    Functionality implied by ID_AA64SMFR0_EL1.SF8DP4 == 0b1.
434
435HWCAP2_POE
436    Functionality implied by ID_AA64MMFR3_EL1.S1POE == 0b0001.
437
4384. Unused AT_HWCAP bits
439-----------------------
440
441For interoperation with userspace, the kernel guarantees that bits 62
442and 63 of AT_HWCAP will always be returned as 0.
443