xref: /linux/Documentation/arch/arm64/elf_hwcaps.rst (revision 79d2e1919a2728ef49d938eb20ebd5903c14dfb0) 
1.. _elf_hwcaps_index:
2
3================
4ARM64 ELF hwcaps
5================
6
7This document describes the usage and semantics of the arm64 ELF hwcaps.
8
9
101. Introduction
11---------------
12
13Some hardware or software features are only available on some CPU
14implementations, and/or with certain kernel configurations, but have no
15architected discovery mechanism available to userspace code at EL0. The
16kernel exposes the presence of these features to userspace through a set
17of flags called hwcaps, exposed in the auxiliary vector.
18
19Userspace software can test for features by acquiring the AT_HWCAP,
20AT_HWCAP2 or AT_HWCAP3 entry of the auxiliary vector, and testing
21whether the relevant flags are set, e.g.::
22
23	bool floating_point_is_present(void)
24	{
25		unsigned long hwcaps = getauxval(AT_HWCAP);
26		if (hwcaps & HWCAP_FP)
27			return true;
28
29		return false;
30	}
31
32Where software relies on a feature described by a hwcap, it should check
33the relevant hwcap flag to verify that the feature is present before
34attempting to make use of the feature.
35
36Features cannot be probed reliably through other means. When a feature
37is not available, attempting to use it may result in unpredictable
38behaviour, and is not guaranteed to result in any reliable indication
39that the feature is unavailable, such as a SIGILL.
40
41
422. Interpretation of hwcaps
43---------------------------
44
45The majority of hwcaps are intended to indicate the presence of features
46which are described by architected ID registers inaccessible to
47userspace code at EL0. These hwcaps are defined in terms of ID register
48fields, and should be interpreted with reference to the definition of
49these fields in the ARM Architecture Reference Manual (ARM ARM).
50
51Such hwcaps are described below in the form::
52
53    Functionality implied by idreg.field == val.
54
55Such hwcaps indicate the availability of functionality that the ARM ARM
56defines as being present when idreg.field has value val, but do not
57indicate that idreg.field is precisely equal to val, nor do they
58indicate the absence of functionality implied by other values of
59idreg.field.
60
61Other hwcaps may indicate the presence of features which cannot be
62described by ID registers alone. These may be described without
63reference to ID registers, and may refer to other documentation.
64
65
663. The hwcaps exposed in AT_HWCAP
67---------------------------------
68
69HWCAP_FP
70    Functionality implied by ID_AA64PFR0_EL1.FP == 0b0000.
71
72HWCAP_ASIMD
73    Functionality implied by ID_AA64PFR0_EL1.AdvSIMD == 0b0000.
74
75HWCAP_EVTSTRM
76    The generic timer is configured to generate events at a frequency of
77    approximately 10KHz.
78
79HWCAP_AES
80    Functionality implied by ID_AA64ISAR0_EL1.AES == 0b0001.
81
82HWCAP_PMULL
83    Functionality implied by ID_AA64ISAR0_EL1.AES == 0b0010.
84
85HWCAP_SHA1
86    Functionality implied by ID_AA64ISAR0_EL1.SHA1 == 0b0001.
87
88HWCAP_SHA2
89    Functionality implied by ID_AA64ISAR0_EL1.SHA2 == 0b0001.
90
91HWCAP_CRC32
92    Functionality implied by ID_AA64ISAR0_EL1.CRC32 == 0b0001.
93
94HWCAP_ATOMICS
95    Functionality implied by ID_AA64ISAR0_EL1.Atomic == 0b0010.
96
97HWCAP_FPHP
98    Functionality implied by ID_AA64PFR0_EL1.FP == 0b0001.
99
100HWCAP_ASIMDHP
101    Functionality implied by ID_AA64PFR0_EL1.AdvSIMD == 0b0001.
102
103HWCAP_CPUID
104    EL0 access to certain ID registers is available, to the extent
105    described by Documentation/arch/arm64/cpu-feature-registers.rst.
106
107    These ID registers may imply the availability of features.
108
109HWCAP_ASIMDRDM
110    Functionality implied by ID_AA64ISAR0_EL1.RDM == 0b0001.
111
112HWCAP_JSCVT
113    Functionality implied by ID_AA64ISAR1_EL1.JSCVT == 0b0001.
114
115HWCAP_FCMA
116    Functionality implied by ID_AA64ISAR1_EL1.FCMA == 0b0001.
117
118HWCAP_LRCPC
119    Functionality implied by ID_AA64ISAR1_EL1.LRCPC == 0b0001.
120
121HWCAP_DCPOP
122    Functionality implied by ID_AA64ISAR1_EL1.DPB == 0b0001.
123
124HWCAP_SHA3
125    Functionality implied by ID_AA64ISAR0_EL1.SHA3 == 0b0001.
126
127HWCAP_SM3
128    Functionality implied by ID_AA64ISAR0_EL1.SM3 == 0b0001.
129
130HWCAP_SM4
131    Functionality implied by ID_AA64ISAR0_EL1.SM4 == 0b0001.
132
133HWCAP_ASIMDDP
134    Functionality implied by ID_AA64ISAR0_EL1.DP == 0b0001.
135
136HWCAP_SHA512
137    Functionality implied by ID_AA64ISAR0_EL1.SHA2 == 0b0010.
138
139HWCAP_SVE
140    Functionality implied by ID_AA64PFR0_EL1.SVE == 0b0001.
141
142HWCAP_ASIMDFHM
143   Functionality implied by ID_AA64ISAR0_EL1.FHM == 0b0001.
144
145HWCAP_DIT
146    Functionality implied by ID_AA64PFR0_EL1.DIT == 0b0001.
147
148HWCAP_USCAT
149    Functionality implied by ID_AA64MMFR2_EL1.AT == 0b0001.
150
151HWCAP_ILRCPC
152    Functionality implied by ID_AA64ISAR1_EL1.LRCPC == 0b0010.
153
154HWCAP_FLAGM
155    Functionality implied by ID_AA64ISAR0_EL1.TS == 0b0001.
156
157HWCAP_SSBS
158    Functionality implied by ID_AA64PFR1_EL1.SSBS == 0b0010.
159
160HWCAP_SB
161    Functionality implied by ID_AA64ISAR1_EL1.SB == 0b0001.
162
163HWCAP_PACA
164    Functionality implied by ID_AA64ISAR1_EL1.APA == 0b0001 or
165    ID_AA64ISAR1_EL1.API == 0b0001, as described by
166    Documentation/arch/arm64/pointer-authentication.rst.
167
168HWCAP_PACG
169    Functionality implied by ID_AA64ISAR1_EL1.GPA == 0b0001 or
170    ID_AA64ISAR1_EL1.GPI == 0b0001, as described by
171    Documentation/arch/arm64/pointer-authentication.rst.
172
173HWCAP_GCS
174    Functionality implied by ID_AA64PFR1_EL1.GCS == 0b1, as
175    described by Documentation/arch/arm64/gcs.rst.
176
177HWCAP2_DCPODP
178    Functionality implied by ID_AA64ISAR1_EL1.DPB == 0b0010.
179
180HWCAP2_SVE2
181    Functionality implied by ID_AA64ZFR0_EL1.SVEver == 0b0001.
182
183HWCAP2_SVEAES
184    Functionality implied by ID_AA64ZFR0_EL1.AES == 0b0001.
185
186HWCAP2_SVEPMULL
187    Functionality implied by ID_AA64ZFR0_EL1.AES == 0b0010.
188
189HWCAP2_SVEBITPERM
190    Functionality implied by ID_AA64ZFR0_EL1.BitPerm == 0b0001.
191
192HWCAP2_SVESHA3
193    Functionality implied by ID_AA64ZFR0_EL1.SHA3 == 0b0001.
194
195HWCAP2_SVESM4
196    Functionality implied by ID_AA64ZFR0_EL1.SM4 == 0b0001.
197
198HWCAP2_FLAGM2
199    Functionality implied by ID_AA64ISAR0_EL1.TS == 0b0010.
200
201HWCAP2_FRINT
202    Functionality implied by ID_AA64ISAR1_EL1.FRINTTS == 0b0001.
203
204HWCAP2_SVEI8MM
205    Functionality implied by ID_AA64ZFR0_EL1.I8MM == 0b0001.
206
207HWCAP2_SVEF32MM
208    Functionality implied by ID_AA64ZFR0_EL1.F32MM == 0b0001.
209
210HWCAP2_SVEF64MM
211    Functionality implied by ID_AA64ZFR0_EL1.F64MM == 0b0001.
212
213HWCAP2_SVEBF16
214    Functionality implied by ID_AA64ZFR0_EL1.BF16 == 0b0001.
215
216HWCAP2_I8MM
217    Functionality implied by ID_AA64ISAR1_EL1.I8MM == 0b0001.
218
219HWCAP2_BF16
220    Functionality implied by ID_AA64ISAR1_EL1.BF16 == 0b0001.
221
222HWCAP2_DGH
223    Functionality implied by ID_AA64ISAR1_EL1.DGH == 0b0001.
224
225HWCAP2_RNG
226    Functionality implied by ID_AA64ISAR0_EL1.RNDR == 0b0001.
227
228HWCAP2_BTI
229    Functionality implied by ID_AA64PFR1_EL1.BT == 0b0001.
230
231HWCAP2_MTE
232    Functionality implied by ID_AA64PFR1_EL1.MTE == 0b0010, as described
233    by Documentation/arch/arm64/memory-tagging-extension.rst.
234
235HWCAP2_ECV
236    Functionality implied by ID_AA64MMFR0_EL1.ECV == 0b0001.
237
238HWCAP2_AFP
239    Functionality implied by ID_AA64MMFR1_EL1.AFP == 0b0001.
240
241HWCAP2_RPRES
242    Functionality implied by ID_AA64ISAR2_EL1.RPRES == 0b0001.
243
244HWCAP2_MTE3
245    Functionality implied by ID_AA64PFR1_EL1.MTE == 0b0011, as described
246    by Documentation/arch/arm64/memory-tagging-extension.rst.
247
248HWCAP2_SME
249    Functionality implied by ID_AA64PFR1_EL1.SME == 0b0001, as described
250    by Documentation/arch/arm64/sme.rst.
251
252HWCAP2_SME_I16I64
253    Functionality implied by ID_AA64SMFR0_EL1.I16I64 == 0b1111.
254
255HWCAP2_SME_F64F64
256    Functionality implied by ID_AA64SMFR0_EL1.F64F64 == 0b1.
257
258HWCAP2_SME_I8I32
259    Functionality implied by ID_AA64SMFR0_EL1.I8I32 == 0b1111.
260
261HWCAP2_SME_F16F32
262    Functionality implied by ID_AA64SMFR0_EL1.F16F32 == 0b1.
263
264HWCAP2_SME_B16F32
265    Functionality implied by ID_AA64SMFR0_EL1.B16F32 == 0b1.
266
267HWCAP2_SME_F32F32
268    Functionality implied by ID_AA64SMFR0_EL1.F32F32 == 0b1.
269
270HWCAP2_SME_FA64
271    Functionality implied by ID_AA64SMFR0_EL1.FA64 == 0b1.
272
273HWCAP2_WFXT
274    Functionality implied by ID_AA64ISAR2_EL1.WFXT == 0b0010.
275
276HWCAP2_EBF16
277    Functionality implied by ID_AA64ISAR1_EL1.BF16 == 0b0010.
278
279HWCAP2_SVE_EBF16
280    Functionality implied by ID_AA64ZFR0_EL1.BF16 == 0b0010.
281
282HWCAP2_CSSC
283    Functionality implied by ID_AA64ISAR2_EL1.CSSC == 0b0001.
284
285HWCAP2_RPRFM
286    Functionality implied by ID_AA64ISAR2_EL1.RPRFM == 0b0001.
287
288HWCAP2_SVE2P1
289    Functionality implied by ID_AA64ZFR0_EL1.SVEver == 0b0010.
290
291HWCAP2_SME2
292    Functionality implied by ID_AA64SMFR0_EL1.SMEver == 0b0001.
293
294HWCAP2_SME2P1
295    Functionality implied by ID_AA64SMFR0_EL1.SMEver == 0b0010.
296
297HWCAP2_SMEI16I32
298    Functionality implied by ID_AA64SMFR0_EL1.I16I32 == 0b0101
299
300HWCAP2_SMEBI32I32
301    Functionality implied by ID_AA64SMFR0_EL1.BI32I32 == 0b1
302
303HWCAP2_SMEB16B16
304    Functionality implied by ID_AA64SMFR0_EL1.B16B16 == 0b1
305
306HWCAP2_SMEF16F16
307    Functionality implied by ID_AA64SMFR0_EL1.F16F16 == 0b1
308
309HWCAP2_MOPS
310    Functionality implied by ID_AA64ISAR2_EL1.MOPS == 0b0001.
311
312HWCAP2_HBC
313    Functionality implied by ID_AA64ISAR2_EL1.BC == 0b0001.
314
315HWCAP2_SVE_B16B16
316    Functionality implied by ID_AA64ZFR0_EL1.B16B16 == 0b0001.
317
318HWCAP2_LRCPC3
319    Functionality implied by ID_AA64ISAR1_EL1.LRCPC == 0b0011.
320
321HWCAP2_LSE128
322    Functionality implied by ID_AA64ISAR0_EL1.Atomic == 0b0011.
323
324HWCAP2_FPMR
325    Functionality implied by ID_AA64PFR2_EL1.FMR == 0b0001.
326
327HWCAP2_LUT
328    Functionality implied by ID_AA64ISAR2_EL1.LUT == 0b0001.
329
330HWCAP2_FAMINMAX
331    Functionality implied by ID_AA64ISAR3_EL1.FAMINMAX == 0b0001.
332
333HWCAP2_F8CVT
334    Functionality implied by ID_AA64FPFR0_EL1.F8CVT == 0b1.
335
336HWCAP2_F8FMA
337    Functionality implied by ID_AA64FPFR0_EL1.F8FMA == 0b1.
338
339HWCAP2_F8DP4
340    Functionality implied by ID_AA64FPFR0_EL1.F8DP4 == 0b1.
341
342HWCAP2_F8DP2
343    Functionality implied by ID_AA64FPFR0_EL1.F8DP2 == 0b1.
344
345HWCAP2_F8E4M3
346    Functionality implied by ID_AA64FPFR0_EL1.F8E4M3 == 0b1.
347
348HWCAP2_F8E5M2
349    Functionality implied by ID_AA64FPFR0_EL1.F8E5M2 == 0b1.
350
351HWCAP2_SME_LUTV2
352    Functionality implied by ID_AA64SMFR0_EL1.LUTv2 == 0b1.
353
354HWCAP2_SME_F8F16
355    Functionality implied by ID_AA64SMFR0_EL1.F8F16 == 0b1.
356
357HWCAP2_SME_F8F32
358    Functionality implied by ID_AA64SMFR0_EL1.F8F32 == 0b1.
359
360HWCAP2_SME_SF8FMA
361    Functionality implied by ID_AA64SMFR0_EL1.SF8FMA == 0b1.
362
363HWCAP2_SME_SF8DP4
364    Functionality implied by ID_AA64SMFR0_EL1.SF8DP4 == 0b1.
365
366HWCAP2_SME_SF8DP2
367    Functionality implied by ID_AA64SMFR0_EL1.SF8DP2 == 0b1.
368
369HWCAP2_SME_SF8DP4
370    Functionality implied by ID_AA64SMFR0_EL1.SF8DP4 == 0b1.
371
372HWCAP2_POE
373    Functionality implied by ID_AA64MMFR3_EL1.S1POE == 0b0001.
374
3754. Unused AT_HWCAP bits
376-----------------------
377
378For interoperation with userspace, the kernel guarantees that bits 62
379and 63 of AT_HWCAP will always be returned as 0.
380