xref: /linux/Documentation/arch/arm64/elf_hwcaps.rst (revision 60a2f25de7b8b785baee2932db932ae9a5b8c86d) 
1.. _elf_hwcaps_index:
2
3================
4ARM64 ELF hwcaps
5================
6
7This document describes the usage and semantics of the arm64 ELF hwcaps.
8
9
101. Introduction
11---------------
12
13Some hardware or software features are only available on some CPU
14implementations, and/or with certain kernel configurations, but have no
15architected discovery mechanism available to userspace code at EL0. The
16kernel exposes the presence of these features to userspace through a set
17of flags called hwcaps, exposed in the auxiliary vector.
18
19Userspace software can test for features by acquiring the AT_HWCAP or
20AT_HWCAP2 entry of the auxiliary vector, and testing whether the relevant
21flags are set, e.g.::
22
23	bool floating_point_is_present(void)
24	{
25		unsigned long hwcaps = getauxval(AT_HWCAP);
26		if (hwcaps & HWCAP_FP)
27			return true;
28
29		return false;
30	}
31
32Where software relies on a feature described by a hwcap, it should check
33the relevant hwcap flag to verify that the feature is present before
34attempting to make use of the feature.
35
36Features cannot be probed reliably through other means. When a feature
37is not available, attempting to use it may result in unpredictable
38behaviour, and is not guaranteed to result in any reliable indication
39that the feature is unavailable, such as a SIGILL.
40
41
422. Interpretation of hwcaps
43---------------------------
44
45The majority of hwcaps are intended to indicate the presence of features
46which are described by architected ID registers inaccessible to
47userspace code at EL0. These hwcaps are defined in terms of ID register
48fields, and should be interpreted with reference to the definition of
49these fields in the ARM Architecture Reference Manual (ARM ARM).
50
51Such hwcaps are described below in the form::
52
53    Functionality implied by idreg.field == val.
54
55Such hwcaps indicate the availability of functionality that the ARM ARM
56defines as being present when idreg.field has value val, but do not
57indicate that idreg.field is precisely equal to val, nor do they
58indicate the absence of functionality implied by other values of
59idreg.field.
60
61Other hwcaps may indicate the presence of features which cannot be
62described by ID registers alone. These may be described without
63reference to ID registers, and may refer to other documentation.
64
65
663. The hwcaps exposed in AT_HWCAP
67---------------------------------
68
69HWCAP_FP
70    Functionality implied by ID_AA64PFR0_EL1.FP == 0b0000.
71
72HWCAP_ASIMD
73    Functionality implied by ID_AA64PFR0_EL1.AdvSIMD == 0b0000.
74
75HWCAP_EVTSTRM
76    The generic timer is configured to generate events at a frequency of
77    approximately 10KHz.
78
79HWCAP_AES
80    Functionality implied by ID_AA64ISAR0_EL1.AES == 0b0001.
81
82HWCAP_PMULL
83    Functionality implied by ID_AA64ISAR0_EL1.AES == 0b0010.
84
85HWCAP_SHA1
86    Functionality implied by ID_AA64ISAR0_EL1.SHA1 == 0b0001.
87
88HWCAP_SHA2
89    Functionality implied by ID_AA64ISAR0_EL1.SHA2 == 0b0001.
90
91HWCAP_CRC32
92    Functionality implied by ID_AA64ISAR0_EL1.CRC32 == 0b0001.
93
94HWCAP_ATOMICS
95    Functionality implied by ID_AA64ISAR0_EL1.Atomic == 0b0010.
96
97HWCAP_FPHP
98    Functionality implied by ID_AA64PFR0_EL1.FP == 0b0001.
99
100HWCAP_ASIMDHP
101    Functionality implied by ID_AA64PFR0_EL1.AdvSIMD == 0b0001.
102
103HWCAP_CPUID
104    EL0 access to certain ID registers is available, to the extent
105    described by Documentation/arch/arm64/cpu-feature-registers.rst.
106
107    These ID registers may imply the availability of features.
108
109HWCAP_ASIMDRDM
110    Functionality implied by ID_AA64ISAR0_EL1.RDM == 0b0001.
111
112HWCAP_JSCVT
113    Functionality implied by ID_AA64ISAR1_EL1.JSCVT == 0b0001.
114
115HWCAP_FCMA
116    Functionality implied by ID_AA64ISAR1_EL1.FCMA == 0b0001.
117
118HWCAP_LRCPC
119    Functionality implied by ID_AA64ISAR1_EL1.LRCPC == 0b0001.
120
121HWCAP_DCPOP
122    Functionality implied by ID_AA64ISAR1_EL1.DPB == 0b0001.
123
124HWCAP_SHA3
125    Functionality implied by ID_AA64ISAR0_EL1.SHA3 == 0b0001.
126
127HWCAP_SM3
128    Functionality implied by ID_AA64ISAR0_EL1.SM3 == 0b0001.
129
130HWCAP_SM4
131    Functionality implied by ID_AA64ISAR0_EL1.SM4 == 0b0001.
132
133HWCAP_ASIMDDP
134    Functionality implied by ID_AA64ISAR0_EL1.DP == 0b0001.
135
136HWCAP_SHA512
137    Functionality implied by ID_AA64ISAR0_EL1.SHA2 == 0b0010.
138
139HWCAP_SVE
140    Functionality implied by ID_AA64PFR0_EL1.SVE == 0b0001.
141
142HWCAP_ASIMDFHM
143   Functionality implied by ID_AA64ISAR0_EL1.FHM == 0b0001.
144
145HWCAP_DIT
146    Functionality implied by ID_AA64PFR0_EL1.DIT == 0b0001.
147
148HWCAP_USCAT
149    Functionality implied by ID_AA64MMFR2_EL1.AT == 0b0001.
150
151HWCAP_ILRCPC
152    Functionality implied by ID_AA64ISAR1_EL1.LRCPC == 0b0010.
153
154HWCAP_FLAGM
155    Functionality implied by ID_AA64ISAR0_EL1.TS == 0b0001.
156
157HWCAP_SSBS
158    Functionality implied by ID_AA64PFR1_EL1.SSBS == 0b0010.
159
160HWCAP_SB
161    Functionality implied by ID_AA64ISAR1_EL1.SB == 0b0001.
162
163HWCAP_PACA
164    Functionality implied by ID_AA64ISAR1_EL1.APA == 0b0001 or
165    ID_AA64ISAR1_EL1.API == 0b0001, as described by
166    Documentation/arch/arm64/pointer-authentication.rst.
167
168HWCAP_PACG
169    Functionality implied by ID_AA64ISAR1_EL1.GPA == 0b0001 or
170    ID_AA64ISAR1_EL1.GPI == 0b0001, as described by
171    Documentation/arch/arm64/pointer-authentication.rst.
172
173HWCAP2_DCPODP
174    Functionality implied by ID_AA64ISAR1_EL1.DPB == 0b0010.
175
176HWCAP2_SVE2
177    Functionality implied by ID_AA64ZFR0_EL1.SVEver == 0b0001.
178
179HWCAP2_SVEAES
180    Functionality implied by ID_AA64ZFR0_EL1.AES == 0b0001.
181
182HWCAP2_SVEPMULL
183    Functionality implied by ID_AA64ZFR0_EL1.AES == 0b0010.
184
185HWCAP2_SVEBITPERM
186    Functionality implied by ID_AA64ZFR0_EL1.BitPerm == 0b0001.
187
188HWCAP2_SVESHA3
189    Functionality implied by ID_AA64ZFR0_EL1.SHA3 == 0b0001.
190
191HWCAP2_SVESM4
192    Functionality implied by ID_AA64ZFR0_EL1.SM4 == 0b0001.
193
194HWCAP2_FLAGM2
195    Functionality implied by ID_AA64ISAR0_EL1.TS == 0b0010.
196
197HWCAP2_FRINT
198    Functionality implied by ID_AA64ISAR1_EL1.FRINTTS == 0b0001.
199
200HWCAP2_SVEI8MM
201    Functionality implied by ID_AA64ZFR0_EL1.I8MM == 0b0001.
202
203HWCAP2_SVEF32MM
204    Functionality implied by ID_AA64ZFR0_EL1.F32MM == 0b0001.
205
206HWCAP2_SVEF64MM
207    Functionality implied by ID_AA64ZFR0_EL1.F64MM == 0b0001.
208
209HWCAP2_SVEBF16
210    Functionality implied by ID_AA64ZFR0_EL1.BF16 == 0b0001.
211
212HWCAP2_I8MM
213    Functionality implied by ID_AA64ISAR1_EL1.I8MM == 0b0001.
214
215HWCAP2_BF16
216    Functionality implied by ID_AA64ISAR1_EL1.BF16 == 0b0001.
217
218HWCAP2_DGH
219    Functionality implied by ID_AA64ISAR1_EL1.DGH == 0b0001.
220
221HWCAP2_RNG
222    Functionality implied by ID_AA64ISAR0_EL1.RNDR == 0b0001.
223
224HWCAP2_BTI
225    Functionality implied by ID_AA64PFR1_EL1.BT == 0b0001.
226
227HWCAP2_MTE
228    Functionality implied by ID_AA64PFR1_EL1.MTE == 0b0010, as described
229    by Documentation/arch/arm64/memory-tagging-extension.rst.
230
231HWCAP2_ECV
232    Functionality implied by ID_AA64MMFR0_EL1.ECV == 0b0001.
233
234HWCAP2_AFP
235    Functionality implied by ID_AA64MMFR1_EL1.AFP == 0b0001.
236
237HWCAP2_RPRES
238    Functionality implied by ID_AA64ISAR2_EL1.RPRES == 0b0001.
239
240HWCAP2_MTE3
241    Functionality implied by ID_AA64PFR1_EL1.MTE == 0b0011, as described
242    by Documentation/arch/arm64/memory-tagging-extension.rst.
243
244HWCAP2_SME
245    Functionality implied by ID_AA64PFR1_EL1.SME == 0b0001, as described
246    by Documentation/arch/arm64/sme.rst.
247
248HWCAP2_SME_I16I64
249    Functionality implied by ID_AA64SMFR0_EL1.I16I64 == 0b1111.
250
251HWCAP2_SME_F64F64
252    Functionality implied by ID_AA64SMFR0_EL1.F64F64 == 0b1.
253
254HWCAP2_SME_I8I32
255    Functionality implied by ID_AA64SMFR0_EL1.I8I32 == 0b1111.
256
257HWCAP2_SME_F16F32
258    Functionality implied by ID_AA64SMFR0_EL1.F16F32 == 0b1.
259
260HWCAP2_SME_B16F32
261    Functionality implied by ID_AA64SMFR0_EL1.B16F32 == 0b1.
262
263HWCAP2_SME_F32F32
264    Functionality implied by ID_AA64SMFR0_EL1.F32F32 == 0b1.
265
266HWCAP2_SME_FA64
267    Functionality implied by ID_AA64SMFR0_EL1.FA64 == 0b1.
268
269HWCAP2_WFXT
270    Functionality implied by ID_AA64ISAR2_EL1.WFXT == 0b0010.
271
272HWCAP2_EBF16
273    Functionality implied by ID_AA64ISAR1_EL1.BF16 == 0b0010.
274
275HWCAP2_SVE_EBF16
276    Functionality implied by ID_AA64ZFR0_EL1.BF16 == 0b0010.
277
278HWCAP2_CSSC
279    Functionality implied by ID_AA64ISAR2_EL1.CSSC == 0b0001.
280
281HWCAP2_RPRFM
282    Functionality implied by ID_AA64ISAR2_EL1.RPRFM == 0b0001.
283
284HWCAP2_SVE2P1
285    Functionality implied by ID_AA64ZFR0_EL1.SVEver == 0b0010.
286
287HWCAP2_SME2
288    Functionality implied by ID_AA64SMFR0_EL1.SMEver == 0b0001.
289
290HWCAP2_SME2P1
291    Functionality implied by ID_AA64SMFR0_EL1.SMEver == 0b0010.
292
293HWCAP2_SMEI16I32
294    Functionality implied by ID_AA64SMFR0_EL1.I16I32 == 0b0101
295
296HWCAP2_SMEBI32I32
297    Functionality implied by ID_AA64SMFR0_EL1.BI32I32 == 0b1
298
299HWCAP2_SMEB16B16
300    Functionality implied by ID_AA64SMFR0_EL1.B16B16 == 0b1
301
302HWCAP2_SMEF16F16
303    Functionality implied by ID_AA64SMFR0_EL1.F16F16 == 0b1
304
305HWCAP2_MOPS
306    Functionality implied by ID_AA64ISAR2_EL1.MOPS == 0b0001.
307
308HWCAP2_HBC
309    Functionality implied by ID_AA64ISAR2_EL1.BC == 0b0001.
310
311HWCAP2_SVE_B16B16
312    Functionality implied by ID_AA64ZFR0_EL1.B16B16 == 0b0001.
313
314HWCAP2_LRCPC3
315    Functionality implied by ID_AA64ISAR1_EL1.LRCPC == 0b0011.
316
317HWCAP2_LSE128
318    Functionality implied by ID_AA64ISAR0_EL1.Atomic == 0b0011.
319
320HWCAP2_FPMR
321    Functionality implied by ID_AA64PFR2_EL1.FMR == 0b0001.
322
323HWCAP2_LUT
324    Functionality implied by ID_AA64ISAR2_EL1.LUT == 0b0001.
325
326HWCAP2_FAMINMAX
327    Functionality implied by ID_AA64ISAR3_EL1.FAMINMAX == 0b0001.
328
329HWCAP2_F8CVT
330    Functionality implied by ID_AA64FPFR0_EL1.F8CVT == 0b1.
331
332HWCAP2_F8FMA
333    Functionality implied by ID_AA64FPFR0_EL1.F8FMA == 0b1.
334
335HWCAP2_F8DP4
336    Functionality implied by ID_AA64FPFR0_EL1.F8DP4 == 0b1.
337
338HWCAP2_F8DP2
339    Functionality implied by ID_AA64FPFR0_EL1.F8DP2 == 0b1.
340
341HWCAP2_F8E4M3
342    Functionality implied by ID_AA64FPFR0_EL1.F8E4M3 == 0b1.
343
344HWCAP2_F8E5M2
345    Functionality implied by ID_AA64FPFR0_EL1.F8E5M2 == 0b1.
346
347HWCAP2_SME_LUTV2
348    Functionality implied by ID_AA64SMFR0_EL1.LUTv2 == 0b1.
349
350HWCAP2_SME_F8F16
351    Functionality implied by ID_AA64SMFR0_EL1.F8F16 == 0b1.
352
353HWCAP2_SME_F8F32
354    Functionality implied by ID_AA64SMFR0_EL1.F8F32 == 0b1.
355
356HWCAP2_SME_SF8FMA
357    Functionality implied by ID_AA64SMFR0_EL1.SF8FMA == 0b1.
358
359HWCAP2_SME_SF8DP4
360    Functionality implied by ID_AA64SMFR0_EL1.SF8DP4 == 0b1.
361
362HWCAP2_SME_SF8DP2
363    Functionality implied by ID_AA64SMFR0_EL1.SF8DP2 == 0b1.
364
365HWCAP2_SME_SF8DP4
366    Functionality implied by ID_AA64SMFR0_EL1.SF8DP4 == 0b1.
367
368
3694. Unused AT_HWCAP bits
370-----------------------
371
372For interoperation with userspace, the kernel guarantees that bits 62
373and 63 of AT_HWCAP will always be returned as 0.
374